Yutaka Masuda

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 28

Top Topics

Energy Minimization

Design Methodology

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Takumi Komori, Yutaka Masuda, Tohru Ishihara
Virtualizing DVFS for Energy Minimization of Embedded Dual-OS Platform. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107 (1) (2024)
Yutaka Masuda, Yusei Honda, Tohru Ishihara
Dynamic Verification Framework of Approximate Computing Circuits using Quality-Aware Coverage-Based Grey-Box Fuzzing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106 (3) (2023)
Yusei Honda, Yutaka Masuda, Tohru Ishihara
Feedback-Tuned Fuzzing for Accelerating Quality Verification of Approximate Computing Design. IOLTS (2023)
Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara
An Efficient Fault Injection Algorithm for Identifying Unimportant FFs in Approximate Computing Circuits. DATE (2023)
Lingxiao Hou, Yutaka Masuda, Tohru Ishihara
An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers for Energy-Efficient Computing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106 (3) (2023)
Tai-Feng Chen, Yutaka Masuda, Tohru Ishihara
A Standard Cell Memory Based on 2T Gain Cell DRAM for Memory-Centric Accelerator Design. SOCC (2023)
Taisei Ichikawa, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi
Optoelectronic Implementation of Compact and Power-efficient Recurrent Neural Networks. ISVLSI (2022)
Lingxiao Hou, Yutaka Masuda, Tohru Ishihara
An Accuracy Reconfigurable Vector Accelerator Based on Approximate Logarithmic Multipliers. ASP-DAC (2022)
TaiYu Cheng, Yutaka Masuda, Jun Nagayama, Yoichi Momiyama, Jun Chen, Masanori Hashimoto
Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2022)
Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto
Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2022)
Takumi Komori, Yutaka Masuda, Jun Shiomi, Tohru Ishihara
Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2022)
Takumi Komori, Yutaka Masuda, Tohru Ishihara
DVFS Virtualization for Energy Minimization of Mixed-Criticality Dual-OS Platforms. RTCSA (2022)
Naoki Hattori, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi
Power-aware pruning for ultrafast, energy-efficient, and accurate optical neural network design. DAC (2022)
Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto
Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design. DATE (2021)
Kazuki Yoshisue, Yutaka Masuda, Tohru Ishihara
Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing. IOLTS (2021)
Takumi Komori, Yutaka Masuda, Jun Shiomi, Tohru Ishihara
Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing. ISQED (2021)
Naoki Hattori, Jun Shiomi, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi
Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2021)
Khyati Kiyawat, Yutaka Masuda, Jun Shiomi, Tohru Ishihara
Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy. ISVLSI (2020)
Tohru Ishihara, Jun Shiomi, Naoki Hattori, Yutaka Masuda, Akihiko Shinya, Masaya Notomi
An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator. PHOTONICS@SC (2019)
Yutaka Masuda, Masanori Hashimoto
MTTF-Aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2019)
Yutaka Masuda, Jun Nagayama, Hirotaka Takeno, Yoshimasa Ogawa, Yoichi Momiyama, Masanori Hashimoto
Comparing voltage adaptation performance between replica and in-situ timing monitors. ICCAD (2018)
Yutaka Masuda, Takao Onoye, Masanori Hashimoto
Activation-Aware Slack Assignment for Time-to-Failure Extension and Power Saving. IEEE Trans. Very Large Scale Integr. Syst. 26 (11) (2018)
Yutaka Masuda, Masanori Hashimoto
MTTF-aware design methodology of error prediction based adaptively voltage-scaled circuits. ASP-DAC (2018)
Yutaka Masuda, Takao Onoye, Masanori Hashimoto
Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2017)
Yutaka Masuda, Masanori Hashimoto, Takao Onoye
Hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms. IOLTS (2016)
Yutaka Masuda, Masanori Hashimoto, Takao Onoye
Critical path isolation for time-to-failure extension and lower voltage operation. ICCAD (2016)
Shoichi Iizuka, Yutaka Masuda, Masanori Hashimoto, Takao Onoye
Stochastic timing error rate estimation under process and temporal variations. ITC (2015)
Yutaka Masuda, Masanori Hashimoto, Takao Onoye
Performance Evaluation of Software-based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise. ICCAD (2015)