On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing.
Hongjie XuJun ShiomiTohru IshiharaHidetoshi OnoderaPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2019)
Keyphrases
- memory access
- memory subsystem
- multithreading
- memory hierarchy
- level parallelism
- memory management
- main memory
- memory bandwidth
- data access
- ibm zenterprise
- instruction set
- cache misses
- shared memory
- random access memory
- processing units
- dynamic random access memory
- parallel computing
- computational power
- speculative execution
- processor core
- embedded dram
- computing power
- cache conscious
- analog vlsi
- external memory
- real time
- data structure
- management system
- vlsi implementation
- data management
- database management systems
- high speed
- operating system
- host computer
- low cost
- query processing
- nm technology
- digital signal processors
- secondary storage
- resource consumption
- hash table