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Analytical Stability Modeling for CMOS Latches in Low Voltage Operation.
Tatsuya Kamakari
Jun Shiomi
Tohru Ishihara
Hidetoshi Onodera
Published in:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2016)
Keyphrases
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low voltage
design considerations
cmos technology
power line
power management
low power
random access memory
power consumption
computer vision
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pattern recognition
digital images
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