Toru Sano

Publication Activity (10 Years)

Years Active: 2008-2020
Publications (10 Years): 2

Top Topics

Object Classification

Top Venues

J. Adv. Comput. Intell. Intell. Informatics

Publications

Yutaka Yamada, Masato Uchiyama, Masashi Jobashi, Tomohiro Koizumi, Takanori Tamai, Nobuhiro Sato, Jun Tanabe, Katsuyuki Kimura, Yoshinari Ojima, Ryusuke Murakami, Takashi Yoshikawa, Toru Sano, Yasuki Tanabe, Yutaro Ishigaki, Soichiro Hosoda, Fumihiko Hyuga, Akira Moriya, Ryuji Hada, Atsushi Masuda
A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications. IEEE J. Solid State Circuits 55 (1) (2020)
Yutaka Yamada, Toru Sano, Yasuki Tanabe, Yutaro Ishigaki, Soichiro Hosoda, Fumihiko Hyuga, Akira Moriya, Ryuji Hada, Atsushi Masuda, Masato Uchiyama, Tomohiro Koizumi, Takanori Tamai, Nobuhiro Sato, Jun Tanabe, Katsuyuki Kimura, Ryusuke Murakami, Takashi Yoshikawa
Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications. ISSCC (2019)
Toru Sano, Yasunori Endo, Shin-ichi Nakazawa, Daisuke Hijikata
On Estimation of Tangential Force in Railways Brake Systems by Fuzzy Inference. J. Adv. Comput. Intell. Intell. Informatics 19 (5) (2015)
Jun Tanabe, Toru Sano, Yutaka Yamada, Tomoki Watanabe, Mayu Okumura, Manabu Nishiyama, Tadakazu Nomura, Kazushige Oma, Nobuhiro Sato, Moriyasu Banno, Hiroo Hayashi, Takashi Miyamori
18.2 A 1.9TOPS and 564GOPS/W heterogeneous multicore SoC with color-based object classification accelerator for image-recognition applications. ISSCC (2015)
Hiroyuki Usui, Jun Tanabe, Toru Sano, Hui Xu, Takashi Miyamori
An evaluation of an energy efficient many-core SoC with parallelized face detection. ASP-DAC (2014)
Takashi Miyamori, Hui Xu, Hiroyuki Usui, Soichiro Hosoda, Toru Sano, Kazumasa Yamamoto, Takeshi Kodaka, Nobuhiro Nonogaki, Nau Ozaki, Jun Tanabe
Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters. IEICE Trans. Electron. (4) (2014)
Takashi Miyamori, Hui Xu, Takeshi Kodaka, Hiroyuki Usui, Toru Sano, Jun Tanabe
Development of low power many-core SoC for multimedia applications. DATE (2013)
Takeshi Kodaka, Akira Takeda, Shunsuke Sasaki, Akira Yokosawa, Toshiki Kizu, Takahiro Tokuyoshi, Hui Xu, Toru Sano, Hiroyuki Usui, Jun Tanabe, Takashi Miyamori, Nobu Matsumoto
A near-future prediction method for low power consumption on a many-core processor. DATE (2013)
Hui Xu, Jun Tanabe, Hiroyuki Usui, Soichiro Hosoda, Toru Sano, Kazumasa Yamamoto, Takeshi Kodaka, Nobuhiro Nonogaki, Nau Ozaki, Takashi Miyamori
A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications. VLSIC (2012)
Kazuei Hironaka, Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano
Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping. FPT (2010)
Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano
MuCCRA-3: a low power dynamically reconfigurable processor array. ASP-DAC (2010)
Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano
MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. FPL (2009)
Toru Sano, Yoshiki Saito, Masaru Kato, Hideharu Amano
Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors. FPL (2009)
Toru Sano, Yoshiki Saito, Hideharu Amano
Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors. ERSA (2009)
Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano
A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array. ERSA (2009)
Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano
Instruction buffer mode for multi-context Dynamically Reconfigurable Processors. FPL (2008)
Takuro Nakamura, Toru Sano, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng, Hideharu Amano
Exploring the optimal size for multicasting configuration data of dynamically reconfigurable processors. FPT (2008)