Takashi Miyamori

Publication Activity (10 Years)

Years Active: 1988-2015
Publications (10 Years): 0

Top Topics

Robust Face Detection

Top Venues

IEICE Trans. Electron.

Publications

Jun Tanabe, Toru Sano, Yutaka Yamada, Tomoki Watanabe, Mayu Okumura, Manabu Nishiyama, Tadakazu Nomura, Kazushige Oma, Nobuhiro Sato, Moriyasu Banno, Hiroo Hayashi, Takashi Miyamori
18.2 A 1.9TOPS and 564GOPS/W heterogeneous multicore SoC with color-based object classification accelerator for image-recognition applications. ISSCC (2015)
Hiroyuki Usui, Jun Tanabe, Toru Sano, Hui Xu, Takashi Miyamori
An evaluation of an energy efficient many-core SoC with parallelized face detection. ASP-DAC (2014)
Takashi Miyamori, Hui Xu, Hiroyuki Usui, Soichiro Hosoda, Toru Sano, Kazumasa Yamamoto, Takeshi Kodaka, Nobuhiro Nonogaki, Nau Ozaki, Jun Tanabe
Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters. IEICE Trans. Electron. (4) (2014)
Takashi Miyamori, Hui Xu, Takeshi Kodaka, Hiroyuki Usui, Toru Sano, Jun Tanabe
Development of low power many-core SoC for multimedia applications. DATE (2013)
Takeshi Kodaka, Akira Takeda, Shunsuke Sasaki, Akira Yokosawa, Toshiki Kizu, Takahiro Tokuyoshi, Hui Xu, Toru Sano, Hiroyuki Usui, Jun Tanabe, Takashi Miyamori, Nobu Matsumoto
A near-future prediction method for low power consumption on a many-core processor. DATE (2013)
Hui Xu, Jun Tanabe, Hiroyuki Usui, Soichiro Hosoda, Toru Sano, Kazumasa Yamamoto, Takeshi Kodaka, Nobuhiro Nonogaki, Nau Ozaki, Takashi Miyamori
A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications. VLSIC (2012)
Yasuki Tanabe, Masato Sumiyoshi, Manabu Nishiyama, Itaru Yamazaki, Shinsuke Fujii, Katsuyuki Kimura, Takuma Aoyama, Moriyasu Banno, Hiroo Hayashi, Takashi Miyamori
A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications. ISSCC (2012)
Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Masatoshi Fukuda, Yasuhiro Koshio, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Hirokazu Ezawa, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Masafumi Takahashi, Yukihito Oowaki
A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM. IEEE J. Solid State Circuits 46 (1) (2011)
Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Yukihito Oowaki
A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm. ISSCC (2010)
Don Draper, Fabio Campi, Ram Krishnamurthy, Takashi Miyamori, Shannon Morton, Willy Sansen, Vladimir Stojanovic, John T. Stonick
Signal and power integrity for SoCs. ISSCC (2010)
Takahisa Wada, Shunichi Ishiwata, Katsuyuki Kimura, Keiri Nakanishi, Masato Sumiyoshi, Takashi Miyamori, Masaki Nakagawa
A VLIW Vector Media Coprocessor With Cascaded SIMD ALUs. IEEE Trans. Very Large Scale Integr. Syst. 17 (9) (2009)
Shuou Nomura, Fumihiko Tachibana, Tetsuya Fujita, Chen Kong Teh, Hiroyuki Usui, Fumiyuki Yamane, Yukimasa Miyamoto, Chaiyasit Kumtornkittikul, Hiroyuki Hara, Takahiro Yamashita, Jun Tanabe, Masaru Uchiyama, Yoshiro Tsuboi, Takashi Miyamori, Takeshi Kitahara, Hironori Sato, Y. Homma, Shuuji Matsumoto, Keiko Seki, Y. Watanabe, Mototsugu Hamada, Makoto Takahashi
A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology. ISSCC (2008)
Takashi Miyamori, Jun Tanabe, Yasuhiro Taniguchi, Kenji Furukawa, Tatsuo Kozakaya, Hiroaki Nakai, Yukimasa Miyamoto, Ken-ichi Maeda, Masataka Matsui
Development of Image Recognition Processor Based on Configurable Processor. J. Robotics Mechatronics 17 (4) (2005)
Shunichi Ishiwata, Tomoo Yamakage, Yoshiro Tsuboi, Takayoshi Shimazawa, Tomoko Kitazawa, Shuji Michinaka, Kunihiko Yahagi, Hideki Takeda, Akihiro Oue, Tomoya Kodama, Nobu Matsumoto, Takayuki Kamei, Mitsuo Saito, Takashi Miyamori, Goichi Ootomo, Masataka Matsui
A single-chip MPEG-2 codec based on customizable media embedded processor. IEEE J. Solid State Circuits 38 (3) (2003)
Jun Tanahe, Yasuhiro Taniguchi, Takashi Miyamori, Yukimasa Miyamoto, Hideki Takeda, Masaya Tarui, Hiromitsu Nakayama, Nohuyulu Takeda, Kenichi Maeda, Masataka Matsui
Visconti: multi-VLIW image recognition processor based on configurable processor [obstacle detection applications]. CICC (2003)
Shunichi Ishiwata, Tomoo Yamakage, Yoshiro Tsuboi, Takayoshi Shimazawa, Tomoko Kitazawa, Shuji Michinaka, Kunihiko Yahagi, Hideki Takeda, Akihiro Oue, Tomoya Kodama, Nobu Matsumoto, Takayuki Kamei, Takashi Miyamori, Goichi Ootomo, Masataka Matsui
A single-chip MPEG-2 codec based on customizable media microprocessor. CICC (2002)
Atsushi Mizuno, Kazuyoshi Kohno, Ryuichiro Ohyama, Takahiro Tokuyoshi, Hironori Uetani, Hans Eichel, Takashi Miyamori, Nobu Matsumoto, Masataka Matsui
Design Methodology and System for a Configurable Media Embedded Processor Extensible to VLIW Architecture. ICCD (2002)
Takashi Miyamori, Kunle Olukotun
A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications. FCCM (1998)
Takashi Miyamori, Kunle Olukotun
REMARC: Reconfigurable Multimedia Array Coprocessor (Abstract). FPGA (1998)
Hidechika Kishigami, Takashi Miyamori, Misao Miyata
The effectiveness of TRONCHIP instructions in the TX1 system. COMPCON (1989)
Kosei Okamoto, Misao Miyata, Hidechika Kishigami, Takashi Miyamori, Tai Sato
Design Considerations for 32-bit Microprocessor TX3. COMPCON (1988)