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A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM.

Yu KikuchiMakoto TakahashiTomohisa MaedaMasatoshi FukudaYasuhiro KoshioHiroyuki HaraHideho ArakidaHideaki YamamotoYousuke HagiwaraTetsuya FujitaManabu WatanabeHirokazu EzawaTakayoshi ShimazawaYasuo OharaTakashi MiyamoriMototsugu HamadaMasafumi TakahashiYukihito Oowaki
Published in: IEEE J. Solid State Circuits (2011)
Keyphrases
  • power consumption
  • real time
  • real world
  • high speed
  • application specific
  • integrated circuit
  • dynamic random access memory