Yukihito Oowaki

Publication Activity (10 Years)

Years Active: 1994-2015
Publications (10 Years): 0

Top Topics

Successive Approximation

Compressive Sensing

Top Venues

IEEE J. Solid State Circuits

Publications

Yosuke Bando, Konosuke Watanabe, Ken-ichi Maeda, Hiroki Kudo, Masahiro Ishiyama, Atsushi Kunimatsu, Hiroto Nakai, Masafumi Takahashi, Yukihito Oowaki
Caching mechanisms towards single-level storage systems for Internet of Things. VLSIC (2015)
Kenta Yasufuku, Naoto Oshiyama, Toshitada Saito, Yukimasa Miyamoto, Yutaka Nakamura, Ryota Terauchi, Atsushi Kondo, Takuma Aoyama, Masafumi Takahashi, Yukihito Oowaki, Ryoichi Bandai
A UHS-II SD card controller with 240MB/s write throughput and 260MB/s read throughput. A-SSCC (2014)
Konosuke Watanabe, Kenichiro Yoshii, Nobuhiro Kondo, Ken-ichi Maeda, Toshio Fujisawa, Junji Wadatsumi, Daisuke Miyashita, Shouhei Kousai, Yasuo Unekawa, Shinsuke Fujii, Takuma Aoyama, Takayuki Tamura, Atsushi Kunimatsu, Yukihito Oowaki
19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension. ISSCC (2014)
Daisuke Miyashita, Ryo Yamaki, Kazunori Hashiyoshi, Hiroyuki Kobayashi, Shouhei Kousai, Yukihito Oowaki, Yasuo Unekawa
An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing. IEEE J. Solid State Circuits 49 (1) (2014)
Daisuke Miyashita, Ryo Yamaki, Kazunori Hashiyoshi, Hiroyuki Kobayashi, Shouhei Kousai, Yukihito Oowaki, Yasuo Unekawa
A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing. ISSCC (2013)
Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Masatoshi Fukuda, Yasuhiro Koshio, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Hirokazu Ezawa, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Masafumi Takahashi, Yukihito Oowaki
A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM. IEEE J. Solid State Circuits 46 (1) (2011)
Yoshiyuki Kitasho, Yu Kikuchi, Takayoshi Shimazawa, Yasuo Ohara, Masafumi Takahashi, Yoshio Masubuchi, Yukihito Oowaki
Development of low power and high performance application processor (T6G) for multimedia mobile applications. ASP-DAC (2011)
Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Yukihito Oowaki
A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm. ISSCC (2010)
Mototsugu Hamada, Takeshi Kitahara, Naoyuki Kawabe, Hironori Sato, Tsuyoshi Nishikawa, Takayoshi Shimazawa, Takahiro Yamashita, Hiroyuki Hara, Yukihito Oowaki
An automated runtime power-gating scheme. ICCD (2007)
Toshihide Fujiyoshi, Shinichiro Shiratake, Shuou Nomura, Tsuyoshi Nishikawa, Yoshiyuki Kitasho, Hideho Arakida, Yuji Okuda, Yoshiro Tsuboi, Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Takayoshi Shimazawa, Kunihiko Yahagi, Hideki Takeda, Masami Murakata, Fumihiro Minami, Naoyuki Kawabe, Takeshi Kitahara, Katsuhiro Seta, Masafumi Takahashi, Yukihito Oowaki, Tohru Furuyama
A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling. IEEE J. Solid State Circuits 41 (1) (2006)
Chen Kong Teh, Mototsugu Hamada, Tetsuya Fujita, Hiroyuki Hara, N. Ikumi, Yukihito Oowaki
Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems. IEEE Trans. Very Large Scale Integr. Syst. 14 (12) (2006)
Yukihito Oowaki, Shinichiro Shiratake, Toshihide Fujiyoshi, Mototsugu Hamada, Fumitoshi Hatori, Masami Murakata, Masafumi Takahashi
Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI. IEICE Trans. Electron. (3) (2006)
Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Chen Kong Teh, Takayoshi Shimazawa, Naoyuki Kawabe, Takeshi Kitahara, Yu Kikuchi, Tsuyoshi Nishikawa, Makoto Takahashi, Yukihito Oowaki
A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI. CICC (2005)
Daisaburo Takashima, Yoshiaki Takeuchi, Tadashi Miyakawa, Yasuo Itoh, Ryu Ogiwara, Masahiro Kamoshida, Katsuhiko Hoya, Sumiko Mano Doumae, Tohru Ozaki, Hiroyuki Kanaya, Koji Yamakawa, Iwao Kunishima, Yukihito Oowaki
8-Mb chain ferroelectric memory. IEEE J. Solid State Circuits 36 (11) (2001)
Daisaburo Takashima, Susumu Shuto, Iwao Kunishima, Hiroyuki Takenaka, Yukihito Oowaki, Shin'ichi Tanaka
A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive. IEEE J. Solid State Circuits 34 (11) (1999)
Daisaburo Takashima, Yukihito Oowaki, Shigeyoshi Watanabe, Kazunori Ohuchi
Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's. IEEE J. Solid State Circuits 33 (2) (1998)
Daisaburo Takashima, Yukihito Oowaki
A novel power-off mode for a battery-backup DRAM. IEEE J. Solid State Circuits 32 (1) (1997)
Daisaburo Takashima, Shigeyoshi Watanabe, Hiroaki Nakano, Yukihito Oowaki, Kazunori Ohuchi
Open/folded bit-line arrangement for ultra-high-density DRAM's. IEEE J. Solid State Circuits 29 (4) (1994)
Daisaburo Takashima, Shigeyoshi Watanabe, Hiroalu Nakano, Yukihito Oowaki, Kazunori Ohuchi, Hiroyuki Tango
Standby/active mode logic for sub-1-V operating ULSI memory. IEEE J. Solid State Circuits 29 (4) (1994)