Naoyuki Kawabe

Publication Activity (10 Years)

Years Active: 2000-2018
Publications (10 Years): 2

Top Topics

Hybrid Architecture

Top Venues

IEEE J. Solid State Circuits

Publications

Kentaro Yoshioka, Hiroshi Kubota, Tomonori Fukushima, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Kaori Watanabe, Yoshinari Ojima, Katsuyuki Kimura, Sohichiroh Hosoda, Yutaka Ota, Tomohiro Koizumi, Naoyuki Kawabe, Yasuhiro Ishii, Yoichiro Iwagami, Seitaro Yagi, Isao Fujisawa, Nobuo Kano, Tomohiro Sugimoto, Daisuke Kurose, Naoya Waki, Yumi Higashi, Tetsuya Nakamura, Yoshikazu Nagashima, Hirotomo Ishii, Akihide Sai, Nobu Matsumoto
A 20ch TDC/ADC hybrid SoC for 240×96-pixel 10%-reflection <0.125%-precision 200m-range imaging LiDAR with smart accumulation technique. ISSCC (2018)
Kentaro Yoshioka, Hiroshi Kubota, Tomonori Fukushima, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Kaori Watanabe, Masatoshi Hirono, Yoshinari Ojima, Katsuyuki Kimura, Sohichiroh Hosoda, Yutaka Ota, Tomohiro Koizumi, Naoyuki Kawabe, Yasuhiro Ishii, Yoichiro Iwagami, Seitaro Yagi, Isao Fujisawa, Nobuo Kano, Tomohiko Sugimoto, Daisuke Kurose, Naoya Waki, Yumi Higashi, Tetsuya Nakamura, Yoshikazu Nagashima, Hirotomo Ishii, Akihide Sai, Nobu Matsumoto
A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 × 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC. IEEE J. Solid State Circuits 53 (11) (2018)
Takeshi Kitahara, Naoyuki Kawabe, Fumihiro Minami, Katsuhiro Seta, Toshiyuki Furusawa
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction CoRR (2007)
Mototsugu Hamada, Takeshi Kitahara, Naoyuki Kawabe, Hironori Sato, Tsuyoshi Nishikawa, Takayoshi Shimazawa, Takahiro Yamashita, Hiroyuki Hara, Yukihito Oowaki
An automated runtime power-gating scheme. ICCD (2007)
Toshihide Fujiyoshi, Shinichiro Shiratake, Shuou Nomura, Tsuyoshi Nishikawa, Yoshiyuki Kitasho, Hideho Arakida, Yuji Okuda, Yoshiro Tsuboi, Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Takayoshi Shimazawa, Kunihiko Yahagi, Hideki Takeda, Masami Murakata, Fumihiro Minami, Naoyuki Kawabe, Takeshi Kitahara, Katsuhiro Seta, Masafumi Takahashi, Yukihito Oowaki, Tohru Furuyama
A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling. IEEE J. Solid State Circuits 41 (1) (2006)
Takeshi Kitahara, Naoyuki Kawabe, Fumihiro Minami, Katsuhiro Seta, Toshiyuki Furusawa
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction. DATE (2005)
Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Chen Kong Teh, Takayoshi Shimazawa, Naoyuki Kawabe, Takeshi Kitahara, Yu Kikuchi, Tsuyoshi Nishikawa, Makoto Takahashi, Yukihito Oowaki
A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI. CICC (2005)
Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa
Selective Multi-Threshold Technique for High-Performance and Low-Standby Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak
Code Coverage-Based Power Estimation Techniques for Microprocessors. J. Circuits Syst. Comput. 11 (5) (2002)
Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa
Automated selective multi-threshold design for ultra-low standby applications. ISLPED (2002)
Naoyuki Kawabe, Kimiyoshi Usami
Low-power technique for on-chip memory using biased partitioning and access concentration. CICC (2000)
Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak
Function-level power estimation methodology for microprocessors. DAC (2000)