Low-power technique for on-chip memory using biased partitioning and access concentration.
Naoyuki KawabeKimiyoshi UsamiPublished in: CICC (2000)
Keyphrases
- low power
- high speed
- low cost
- power dissipation
- single chip
- low power consumption
- power consumption
- mixed signal
- cmos technology
- nm technology
- ultra low power
- high power
- random access
- storage devices
- memory access
- signal processor
- digital signal processing
- image sensor
- power reduction
- vlsi circuits
- logic circuits
- access control
- vlsi architecture
- wireless transmission
- real time
- main memory
- high density
- cmos image sensor