Hiroyuki Takenaka

Publication Activity (10 Years)

Years Active: 1999-2008
Publications (10 Years): 0

Publications

Mariko Kaku, Hitoshi Iwai, Takeshi Nagai, Masaharu Wada, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Takayuki Iwai, Hiroyuki Takenaka, Takehiko Hojo, Shinji Miyano, Nobuaki Otsuka
An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications. ISSCC (2008)
Takeshi Nagai, Masaharu Wada, Hitoshi Iwai, Mariko Kaku, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Hiroyuki Takenaka, Takehiko Hojo, Shinji Miyano
A 65nm low-power embedded DRAM with extended data-retention sleep mode. ISSCC (2006)
Ryo Haga, Tetsuya Kaneko, Atsushi Nakayama, Shinji Miyano, Hiroyuki Takenaka, Kenji Numata, Hiroyuki Koinuma, Takehiko Hojo, Akikuni Sato, Toshiyuki Kouchi, Kenichiro Mimoto, Masaaki Tazawa, Tsutomu Ohkubo, Takanori Andou, Tetsuya Amano
Interface socket design methodology to generate embedded DRAM macros. CICC (2001)
Ryu Ogiwara, Sumio Tanaka, Yasuo Itoh, Tadashi Miyakawa, Yoshiaki Takeuchi, Sumiko Mano Doumae, Hiroyuki Takenaka, Iwao Kunishima, Susumu Shuto, Osamu Hidaka, Sumito Ohtsuki, Shin'ichi Tanaka
A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor. IEEE J. Solid State Circuits 35 (4) (2000)
Daisaburo Takashima, Susumu Shuto, Iwao Kunishima, Hiroyuki Takenaka, Yukihito Oowaki, Shin'ichi Tanaka
A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive. IEEE J. Solid State Circuits 34 (11) (1999)