Masaharu Wada

Publication Activity (10 Years)

Years Active: 1993-2008
Publications (10 Years): 0

Publications

Mariko Kaku, Hitoshi Iwai, Takeshi Nagai, Masaharu Wada, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Takayuki Iwai, Hiroyuki Takenaka, Takehiko Hojo, Shinji Miyano, Nobuaki Otsuka
An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications. ISSCC (2008)
Takeshi Nagai, Masaharu Wada, Hitoshi Iwai, Mariko Kaku, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Hiroyuki Takenaka, Takehiko Hojo, Shinji Miyano
A 65nm low-power embedded DRAM with extended data-retention sleep mode. ISSCC (2006)
Tomoaki Yabe, Shinji Miyano, Katsuhiko Sato, Masaharu Wada, Ryo Haga, Osamu Wada, Motohiro Enkaku, Takehiko Hojyo, Kenichiro Mimoto, Masaaki Tazawa, Tsutomu Ohkubo, Kenji Numata
A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator. IEEE J. Solid State Circuits 33 (11) (1998)
Shinji Miyano, Kenji Numata, Katsuhiko Sato, Tomoaki Yabe, Masaharu Wada, Ryo Haga, Motohiro Enkaku, Masazumi Shiochi, Yutaka Kawashima, Masayuki Iwase, Masahisa Ohgata, Junpei Kumagai, Takeshi Yoshida, Masaomi Sakurai, Seiji Kaki, Narutoshi Yanagiya, Hiroshi Shinya, Tohm Fumyama, Paul Hansen, Marc Hannah, Michael Nagy, Anan Nagarajan, Mana Rungsea
A 1.6 Gbyte/s data transfer rate 8 Mb embedded DRAM. IEEE J. Solid State Circuits 30 (11) (1995)
Masaharu Wada
Proposal for fully automated mail processing system for the 21st century. Pattern Recognit. Lett. 14 (4) (1993)