A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor.
Ryu OgiwaraSumio TanakaYasuo ItohTadashi MiyakawaYoshiaki TakeuchiSumiko Mano DoumaeHiroyuki TakenakaIwao KunishimaSusumu ShutoOsamu HidakaSumito OhtsukiShin'ichi TanakaPublished in: IEEE J. Solid State Circuits (2000)