Yutaka Yamada

Publication Activity (10 Years)

Years Active: 2004-2022
Publications (10 Years): 4

Top Topics

Object Classification

Top Venues

IEEE J. Solid State Circuits

Publications

Yutaka Yamada, Keisuke Maeda, Takahiro Ogawa, Miki Haseyama
Trend Prediction of Students' Mock Examination Results Using Matrix Completion. GCCE (2022)
Yutaka Yamada, Masato Uchiyama, Masashi Jobashi, Tomohiro Koizumi, Takanori Tamai, Nobuhiro Sato, Jun Tanabe, Katsuyuki Kimura, Yoshinari Ojima, Ryusuke Murakami, Takashi Yoshikawa, Toru Sano, Yasuki Tanabe, Yutaro Ishigaki, Soichiro Hosoda, Fumihiko Hyuga, Akira Moriya, Ryuji Hada, Atsushi Masuda
A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications. IEEE J. Solid State Circuits 55 (1) (2020)
Yutaka Yamada, Toru Sano, Yasuki Tanabe, Yutaro Ishigaki, Soichiro Hosoda, Fumihiko Hyuga, Akira Moriya, Ryuji Hada, Atsushi Masuda, Masato Uchiyama, Tomohiro Koizumi, Takanori Tamai, Nobuhiro Sato, Jun Tanabe, Katsuyuki Kimura, Ryusuke Murakami, Takashi Yoshikawa
Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications. ISSCC (2019)
Yutaka Yamada, Takahiro Ogawa, Miki Haseyama
Performance Prediction Method of Examinees Based on Matrix Completion. GCCE (2019)
Jun Tanabe, Toru Sano, Yutaka Yamada, Tomoki Watanabe, Mayu Okumura, Manabu Nishiyama, Tadakazu Nomura, Kazushige Oma, Nobuhiro Sato, Moriyasu Banno, Hiroo Hayashi, Takashi Miyamori
18.2 A 1.9TOPS and 564GOPS/W heterogeneous multicore SoC with color-based object classification accelerator for image-recognition applications. ISSCC (2015)
Takashi Yoshikawa, Fumihiko Hyuga, Masayuki Tokunaga, Yutaka Yamada, Shigehiro Asano
FlexGrip™: A small and high-performance programmable hardware for highly sequential application. COOL Chips (2011)
Toshiyuki Harada, Yoshiaki Nakagawa, Takehiko Ogura, Yutaka Yamada, Takehiro Ohe, Hisashi Miyagawa
Virtual Screening for Ligands of the Insect Molting Hormone Receptor. J. Chem. Inf. Model. 51 (2) (2011)
Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano
Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. IEEE Trans. Parallel Distributed Syst. 20 (8) (2009)
Takashi Yoshikawa, Yutaka Yamada, Shigehiro Asano
An implementation of hardware accelerator using dynamically reconfigurable architecture. Hot Chips Symposium (2006)
Michihiro Koibuchi, Kenichiro Anjo, Yutaka Yamada, Akiya Jouraku, Hideharu Amano
A Simple Data Transfer Technique Using Local Address for Networks-on-Chips. IEEE Trans. Parallel Distributed Syst. 17 (12) (2006)
Nobuaki Kamimoto, Yutaka Yamada, Masami Kitamura, Kiyoshi Nishikawa
Evaluation of vibration in many positions by SOM. Artif. Life Robotics 9 (1) (2005)
Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano
Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips. ICPP Workshops (2005)
Masayasu Suzuki, Yohei Hasegawa, Yutaka Yamada, Naoto Kaneko, Katsuaki Deguchi, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takao Toi, Toru Awashima
Stream applications on the dynamically reconfigurable processor. FPT (2004)
Kenichiro Anjo, Yutaka Yamada, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano
BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips. IPDPS (2004)
Yutaka Yamada, Hideharu Amano, Michihiro Koibuchi, Akiya Jouraku, Kenichiro Anjo, Katsunobu Nishimura
Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array. EUC (2004)
Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor. FCCM (2004)