An implementation of hardware accelerator using dynamically reconfigurable architecture.
Takashi YoshikawaYutaka YamadaShigehiro AsanoPublished in: Hot Chips Symposium (2006)
Keyphrases
- reconfigurable architecture
- hardware implementation
- hardware architecture
- graphics cards
- real time
- systolic array
- parallel implementation
- dedicated hardware
- vlsi implementation
- software implementation
- hardware and software
- circuit design
- high level language
- parallel architecture
- computing platform
- computer architecture
- graph cuts
- higher order
- pattern recognition
- image processing