A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors.
Yasuhisa ShimazakiNoriyuki MiuraTadahiro KurodaPublished in: COOL Chips (2012)
Keyphrases
- design methodology
- chip design
- physical design
- cmos technology
- power dissipation
- nm technology
- parallel processing
- analog vlsi
- low cost
- silicon on insulator
- high speed
- metal oxide semiconductor
- design process
- low power
- power consumption
- circuit design
- object oriented
- design methodologies
- cmos image sensor
- user interface
- fuzzy neural network
- image sensor
- formal specification
- low voltage
- single chip
- parallel algorithm
- databases
- random access memory
- computational intelligence