Nidhal Selmane

Publication Activity (10 Years)

Years Active: 2008-2011
Publications (10 Years): 0

Télécom ParisTech, France (PHD)

Education History

Télécom ParisTech, France

PHD

Publications

Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Denis Réal
Performance evaluation of protocols resilient to physical attacks. HOST (2011)
Nidhal Selmane, Shivam Bhasin, Sylvain Guilley, Jean-Luc Danger
Security evaluation of application-specific integrated circuits and field programmable gate arrays against setup time violation attacks. IET Inf. Secur. 5 (4) (2011)
Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane
Fault Injection Resilience. FDTC (2010)
Shivam Bhasin, Sylvain Guilley, Florent Flament, Nidhal Selmane, Jean-Luc Danger
Countering early evaluation: an approach towards robust dual-rail precharge logic. WESS (2010)
Nidhal Selmane, Shivam Bhasin, Sylvain Guilley, Tarik Graba, Jean-Luc Danger
WDDL is Protected against Setup Time Violation Attacks. FDTC (2009)
Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Nidhal Selmane
Security Evaluation of Different AES Implementations Against Practical Setup Time Violation Attacks in FPGAs. HOST (2009)
Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. ReConFig (2009)
Farouk Khelil, Mohamed Hamdi, Sylvain Guilley, Jean-Luc Danger, Nidhal Selmane
Fault Analysis Attack on an FPGA AES Implementation. NTMS (2008)
Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Renaud Pacalet
Silicon-level Solutions to Counteract Passive and Active Attacks. FDTC (2008)
Nidhal Selmane, Sylvain Guilley, Jean-Luc Danger
Practical Setup Time Violation Attacks on AES. EDCC (2008)

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Publication Activity (10 Years)

Nidhal Selmane