Laurent Sauvage

Publication Activity (10 Years)

Years Active: 2008-2024
Publications (10 Years): 15

Top Topics

Countermeasures

Top Venues

IACR Cryptol. ePrint Arch.

J. Cryptogr. Eng.

Publications

Maxime Spyropoulos, David Vigilant, Fabrice Perion, Renaud Pacalet, Laurent Sauvage
Masked Vector Sampling for HQC. IACR Cryptol. ePrint Arch. 2024 (2024)
Roukoz Nabhan, Jean-Max Dutertre, Jean-Baptiste Rigaud, Jean-Luc Danger, Laurent Sauvage
EM Fault Injection-Induced Clock Glitches: From Mechanism Analysis to Novel Sensor Design. IOLTS (2024)
Roukoz Nabhan, Jean-Max Dutertre, Jean-Baptiste Rigaud, Jean-Luc Danger, Laurent Sauvage
A Tale of Two Models: Discussing the Timing and Sampling EM Fault Injection Models. FDTC (2023)
Roukoz Nabhan, Jean-Max Dutertre, Jean-Baptiste Rigaud, Jean-Luc Danger, Laurent Sauvage
Highlighting Two EM Fault Models While Analyzing a Digital Sensor Limitations. DATE (2023)
Arnaud Varillon, Laurent Sauvage, Jean-Luc Danger
High-Order Collision Attack Vulnerabilities in Montgomery Ladder Implementations of RSA. SPACE (2023)
Pierre-Augustin Berthet, Cédric Tavernier, Jean-Luc Danger, Laurent Sauvage
Quasi-linear Masking to Protect Kyber against both SCA and FIA. IACR Cryptol. ePrint Arch. 2023 (2023)
Yohaï-Eliel Berreby, Laurent Sauvage
Investigating Efficient Deep Learning Architectures For Side-Channel Attacks on AES. CoRR (2023)
Sofiane Takarabt, Sylvain Guilley, Youssef Souissi, Khaled Karray, Laurent Sauvage, Yves Mathieu
Formal Evaluation and Construction of Glitch-resistant Masked Functions. HOST (2021)
Oualid Trabelsi, Laurent Sauvage, Jean-Luc Danger
Characterization of Electromagnetic Fault Injection on a 32-bit Microcontroller Instruction Buffer. AsianHOST (2020)
Sofiane Takarabt, Alexander Schaub, Adrien Facon, Sylvain Guilley, Laurent Sauvage, Youssef Souissi, Yves Mathieu
Cache-Timing Attacks Still Threaten IoT Devices. C2SI (2019)
Sofiane Takarabt, Kais Chibani, Adrien Facon, Sylvain Guilley, Yves Mathieu, Laurent Sauvage, Youssef Souissi
Pre-silicon Embedded System Evaluation as New EDA Tool for Security Verification. IVSW (2018)
Wei Cheng, Chao Zheng, Yuchen Cao, Yongbin Zhou, Hailong Zhang, Sylvain Guilley, Laurent Sauvage
How Far Can We Reach? Breaking RSM-Masked AES-128 Implementation Using Only One Trace. IACR Cryptol. ePrint Arch. 2017 (2017)
Laurent Sauvage, Tarik Graba, Thibault Porteboeuf
Multi-level formal verification - A new approach against fault injection attack. J. Cryptogr. Eng. 7 (1) (2017)
Kazuhide Fukushima, Youssef Souissi, Seira Hidano, Robert Nguyen, Jean-Luc Danger, Sylvain Guilley, Yuto Nakano, Shinsaku Kiyomoto, Laurent Sauvage
Delay PUF Assessment Method Based on Side-Channel and Modeling Analyzes: The Final Piece of All-in-One Assessment Methodology. Trustcom/BigDataSE/ISPA (2016)
Wei Cheng, Yongbin Zhou, Laurent Sauvage
Differential Fault Analysis on Midori. ICICS (2016)
Lionel Rivière, Zakaria Najm, Pablo Rauzy, Jean-Luc Danger, Julien Bringer, Laurent Sauvage
High Precision Fault Injections on the Instruction Cache of ARMv7-M Architectures. IACR Cryptol. ePrint Arch. 2015 (2015)
Lionel Rivière, Zakaria Najm, Pablo Rauzy, Jean-Luc Danger, Julien Bringer, Laurent Sauvage
High precision fault injections on the instruction cache of ARMv7-M architectures. HOST (2015)
Lionel Rivière, Zakaria Najm, Pablo Rauzy, Jean-Luc Danger, Julien Bringer, Laurent Sauvage
High Precision Fault Injections on the Instruction Cache of ARMv7-M Architectures. CoRR (2015)
Christophe Clavier, Jean-Luc Danger, Guillaume Duc, M. Abdelaziz Elaabid, Benoît Gérard, Sylvain Guilley, Annelie Heuser, Michael Kasper, Yang Li, Victor Lomné, Daisuke Nakatsu, Kazuo Ohta, Kazuo Sakiyama, Laurent Sauvage, Werner Schindler, Marc Stöttinger, Nicolas Veyrat-Charvillon, Matthieu Walle, Antoine Wurcker
Practical improvements of side-channel attacks on AES: feedback from the 2nd DPA contest. J. Cryptogr. Eng. 4 (4) (2014)
Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Xuan Thuy Ngo, Laurent Sauvage
Hardware Trojan Horses in Cryptographic IP Cores. IACR Cryptol. ePrint Arch. 2014 (2014)
Yuto Nakano, Youssef Souissi, Robert Nguyen, Laurent Sauvage, Jean-Luc Danger, Sylvain Guilley, Shinsaku Kiyomoto, Yutaka Miyake
A Pre-processing Composition for Secret Key Recovery on Android Smartphone. WISTP (2014)
Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Xuan Thuy Ngo, Laurent Sauvage
Hardware Trojan Horses in Cryptographic IP Cores. FDTC (2013)
Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu
Blind Cartography for Side Channel Attacks: Cross-Correlation Cartography. Int. J. Reconfigurable Comput. 2012 (2012)
Taoufik Chouta, Jean-Luc Danger, Laurent Sauvage, Tarik Graba
A Small and High-Performance Coprocessor for Fingerprint Match-on-Card. DSD (2012)
Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Denis Réal
Performance evaluation of protocols resilient to physical attacks. HOST (2011)
Olivier Meynard, Sylvain Guilley, Jean-Luc Danger, Laurent Sauvage
Far Correlation-based EMA with a precharacterized leakage model. DATE (2010)
Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu
Cross-Correlation Cartography. ReConFig (2010)
Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu
Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics. Int. J. Reconfigurable Comput. 2010 (2010)
Sylvain Guilley, Laurent Sauvage, Julien Micolod, Denis Réal, Frédéric Valette
Defeating Any Secret Cryptography with SCARE Attacks. LATINCRYPT (2010)
Shivam Bhasin, Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger
Unrolling Cryptographic Circuits: A Simple Countermeasure Against Side-Channel Attacks. CT-RSA (2010)
Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane
Fault Injection Resilience. FDTC (2010)
Sylvain Guilley, Laurent Sauvage, Florent Flament, Vinh-Nga Vong, Philippe Hoogvorst, Renaud Pacalet
Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics. IEEE Trans. Computers 59 (9) (2010)
Laurent Sauvage, Sylvain Guilley, Yves Mathieu
Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack on a Cryptographic Module. ACM Trans. Reconfigurable Technol. Syst. 2 (1) (2009)
Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints. DATE (2009)
Sylvain Guilley, Sumanta Chaudhuri, Laurent Sauvage, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet
Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks. ICECS (2009)
Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu
DPL on Stratix II FPGA: What to Expect?. ReConFig (2009)
Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. ReConFig (2009)
Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Philippe Hoogvorst
Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic. FPL (2008)
Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Tarik Graba, Yves Mathieu
Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs. SSIRI (2008)
Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Laurent Sauvage, Philippe Hoogvorst, Maxime Nassar, Tarik Graba, Vinh-Nga Vong
Place-and-Route Impact on the Security of DPL Designs in FPGAs. HOST (2008)
Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Renaud Pacalet
Silicon-level Solutions to Counteract Passive and Active Attacks. FDTC (2008)
Sylvain Guilley, Laurent Sauvage, Philippe Hoogvorst, Renaud Pacalet, Guido Marco Bertoni, Sumanta Chaudhuri
Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks. IEEE Trans. Computers 57 (11) (2008)