Sumanta Chaudhuri

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 12

Top Topics

Back Propagation

Digital Image Watermarking

Top Venues

IEICE Electron. Express

Publications

Carl De Sousa Trias, Mihai Petru Mitrea, Attilio Fiandrotti, Marco Cagnazzo, Sumanta Chaudhuri, Enzo Tartaglione
Find the Lady: Permutation and Re-synchronization of Deep Neural Networks. AAAI (2024)
Quentin Forcioli, Sumanta Chaudhuri, Jean-Luc Danger
TEE-Time: A Dynamic Cache Timing Analysis Tool for Trusted Execution Environments. ISQED (2024)
Carl De Sousa Trias, Mihai Petru Mitrea, Attilio Fiandrotti, Marco Cagnazzo, Sumanta Chaudhuri, Enzo Tartaglione
Find the Lady: Permutation and Re-Synchronization of Deep Neural Networks. CoRR (2023)
Carl De Sousa Trias, Mihai Mitrea, Enzo Tartaglione, Attilio Fiandrotti, Marco Cagnazzo, Sumanta Chaudhuri
A Hitchhiker's Guide to White-Box Neural Network Watermarking Robustness. EUVIP (2023)
Quentin Forcioli, Jean-Luc Danger, Sumanta Chaudhuri
A gem5 based Platform for Micro-Architectural Security Analysis. HASP@MICRO (2023)
Xuecan Yang, Sumanta Chaudhuri, Laurence Likforman, Lirida A. B. Naviner
Minconvnets: a New Class of Multiplication-Less Neural Networks. ICIP (2022)
Xuecan Yang, Sumanta Chaudhuri, Laurence Likforman, Lirida A. B. Naviner
MinConvNets: A new class of multiplication-less Neural Networks. CoRR (2021)
Xuecan Yang, Sumanta Chaudhuri, Lirida A. B. Naviner, Laurence Likforman
Quad-Approx CNNs for Embedded Object Detection Systems. ICECS (2020)
Sumanta Chaudhuri
Beyond Bits: A Quaternary FPGA Architecture Using Multi-Vt Multi-Vdd FDSOI Devices. ISMVL (2018)
Sumanta Chaudhuri
A security vulnerability analysis of SoCFPGA architectures. DAC (2018)
Sumanta Chaudhuri
Cache Timing Attacks from The SoCFPGA Coherency Port (Abstract Only). FPGA (2017)
Sumanta Chaudhuri, Tarik Graba, Yves Mathieu
Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology. CoRR (2016)
Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
Classification on variation maps: a new placement strategy to alleviate process variation on FPGA. IEICE Electron. Express 11 (3) (2014)
Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
Mitigation of process variation effect in FPGAs with partial rerouting method. IEICE Electron. Express 11 (3) (2014)
Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
A variation-adaptive retiming method exploiting reconfigurability. FPL (2013)
Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting. FPT (2013)
Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
A two-stage variation-aware placement method for FPGAS exploiting variation maps classification. FPL (2012)
Weisheng Zhao, Sumanta Chaudhuri, Celso Accoto, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer
Cross-point architecture for spin transfer torque magnetic random access memory CoRR (2012)
Sumanta Chaudhuri, Sylvain Guilley
Side-Channel Oscilloscope CoRR (2011)
Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin
A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback CoRR (2011)
Sumanta Chaudhuri, Justin S. J. Wong, Peter Y. K. Cheung
Timing speculation in FPGAs: Probabilistic inference of data dependent failure rates. FPT (2011)
Sumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer
High Density Asynchronous LUT Based on Non-volatile MRAM Technology. FPL (2010)
Sumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer
Design of embedded MRAM macros for memory-in-logic applications. ACM Great Lakes Symposium on VLSI (2010)
Sylvain Guilley, Sumanta Chaudhuri, Laurent Sauvage, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet
Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks. ICECS (2009)
Sumanta Chaudhuri
Diagonal tracks in FPGAs: a performance evaluation. FPGA (2009)
Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin
Physical Design of FPGA Interconnect to Prevent Information Leakage. ARC (2008)
Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger
Efficient tiling patterns for reconfigurable gate arrays. SLIP (2008)
Sumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst, Sylvain Guilley
Efficient tiling patterns for reconfigurable gate arrays. FPGA (2008)
Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Laurent Sauvage, Philippe Hoogvorst, Maxime Nassar, Tarik Graba, Vinh-Nga Vong
Place-and-Route Impact on the Security of DPL Designs in FPGAs. HOST (2008)
Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet
A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks CoRR (2008)
Sumanta Chaudhuri, Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Jean-Luc Danger
An 8x8 run-time reconfigurable FPGA embedded in a SoC. DAC (2008)
Sylvain Guilley, Laurent Sauvage, Philippe Hoogvorst, Renaud Pacalet, Guido Marco Bertoni, Sumanta Chaudhuri
Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks. IEEE Trans. Computers 57 (11) (2008)
Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin, Sumanta Chaudhuri, Sylvain Guilley, Jean-Luc Danger, Philippe Hoogvorst
A Novel Asynchronous e-FPGA Architecture for Security Applications. FPT (2007)
Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Alin Razafindraibe, Taha Beyrouthy, Laurent Fesquet
A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. ReCoSoC (2007)
Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley
Efficient Modeling and Floorplanning of Embedded-FPGA Fabric. FPL (2007)
Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst
FASE: An Open Run-Time Reconfigurable FPGA Architecture for Tamper-Resistant and Secure Embedded Systems. ReConFig (2006)