Alin Razafindraibe

Publication Activity (10 Years)

Years Active: 2005-2011
Publications (10 Years): 0

Publications

Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin
A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback CoRR (2011)
Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin
Physical Design of FPGA Interconnect to Prevent Information Leakage. ARC (2008)
Alin Razafindraibe, Philippe Maurine
A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates. PATMOS (2007)
Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin, Sumanta Chaudhuri, Sylvain Guilley, Jean-Luc Danger, Philippe Hoogvorst
A Novel Asynchronous e-FPGA Architecture for Security Applications. FPT (2007)
Alin Razafindraibe, Michel Robert, Philippe Maurine
Improvement of dual rail logic as a countermeasure against DPA. VLSI-SoC (2007)
Alin Razafindraibe, Michel Robert, Philippe Maurine
Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA. PATMOS (2007)
Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Alin Razafindraibe, Taha Beyrouthy, Laurent Fesquet
A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. ReCoSoC (2007)
Alin Razafindraibe, Michel Robert, Philippe Maurine
Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks. PATMOS (2006)
Alin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin
Security evaluation of dual rail logic against DPA attacks. VLSI-SoC (2006)
Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine
A Method to Design Compact Dual-rail Asynchronous Primitives. PATMOS (2005)
Alin Razafindraibe, Michel Robert, Philippe Maurine
Compact and Secured Primitives for the Design of Asynchronous Circuits. J. Low Power Electron. 1 (1) (2005)