Countering early propagation and routing imbalance of DPL designs in a tree-based FPGA.
Emna AmouriShivam BhasinYves MathieuTarik GrabaJean-Luc DangerPublished in: ICICDT (2015)
Keyphrases
- hardware implementation
- high speed
- network topology
- routing protocol
- routing algorithm
- image processing
- low cost
- class imbalance
- ad hoc networks
- single chip
- software implementation
- routing problem
- signal processing
- real time image processing
- fpga implementation
- real time
- digital signal
- hardware design
- field programmable gate array
- class distribution
- data sets
- imbalanced datasets
- network topologies
- design space
- peer to peer
- wave propagation
- propagation model
- power reduction