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BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation.
Maxime Nassar
Shivam Bhasin
Jean-Luc Danger
Guillaume Duc
Sylvain Guilley
Published in:
DATE (2010)
Keyphrases
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high speed
low power
low cost
data mining
data acquisition
signal processing
high speed networks
evaluation methods
real time
image processing
computer vision
neural network
multiscale
embedded systems
evaluation method
machine learning
comparative evaluation
field programmable gate array
single chip