Wei He

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 5

Top Topics

Routing Problem

Linear Time Temporal Logic

Top Venues

IACR Trans. Cryptogr. Hardw. Embed. Syst.

Microprocess. Microsystems

IEEE Trans. Computers

Publications

Bo Yu, Huajie Shen, Qian Xu, Wei He, Wankui Mao, Qing Zhang, Fan Zhang
HQsFL: A Novel Training Strategy for Constructing High-performance and Quantum-safe Federated Learning. AsiaCCS (2024)
Zixiao Wang, Biyao Che, Liang Guo, Yang Du, Ying Chen, Jizhuang Zhao, Wei He
PipeFL: Hardware/Software co-Design of an FPGA Accelerator for Federated Learning. IEEE Access 10 (2022)
Guorui Xu, Fan Zhang, Bolin Yang, Xinjie Zhao, Wei He, Kui Ren
Pushing the Limit of PFA: Enhanced Persistent Fault Analysis on Block Ciphers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (6) (2021)
Fan Zhang, Bolin Yang, Xiaofei Dong, Sylvain Guilley, Zhe Liu, Wei He, Fangguo Zhang, Kui Ren
Side-Channel Analysis and Countermeasure Design on ARM-Based Quantum-Resistant SIKE. IEEE Trans. Computers 69 (11) (2020)
Fan Zhang, Xiaoxuan Lou, Xinjie Zhao, Shivam Bhasin, Wei He, Ruyi Ding, Samiya Qureshi, Kui Ren
Persistent Fault Analysis on Block Ciphers. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2018 (3) (2018)
Wei He, Shivam Bhasin, Andrés Otero, Tarik Graba, Eduardo de la Torre, Jean-Luc Danger
Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis. IET Inf. Secur. 9 (1) (2015)
Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic. Microprocess. Microsystems 38 (8) (2014)
Wei He, Eduardo de la Torre, Teresa Riesgo
An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation. COSADE (2012)
Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
Automatic generation of identical routing pairs for FPGA implemented DPL logic. ReConFig (2012)
Wei He, Eduardo de la Torre, Teresa Riesgo
A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations. ReConFig (2011)