Yana Esteves Krasteva

Publication Activity (10 Years)

Years Active: 2005-2010
Publications (10 Years): 0

Publications

Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo
Reconfigurable Networks on Chip: DRNoC architecture. J. Syst. Archit. 56 (7) (2010)
Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Yana Esteves Krasteva
Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs. FPL (2010)
Andrés Otero, Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo
Generic Systolic Array for Run-Time Scalable Cores. ARC (2010)
Yana Esteves Krasteva, Francisco Criado, Eduardo de la Torre, Teresa Riesgo
A Fast Emulation-Based NoC Prototyping Framework. ReConFig (2008)
Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo
Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management. ISCAS (2007)
Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo
Partial Reconfiguration for Core Reallocation and Flexible Communications. ReCoSoC (2006)
Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo, Didier Joly
Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems. FPL (2006)
Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo
Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs. IEEE International Workshop on Rapid System Prototyping (2005)
Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo
Flexible Core Reallocation for Virtex II Structures. ERSA (2005)