Reconfigurable Networks on Chip: DRNoC architecture.
Yana Esteves KrastevaEduardo de la TorreTeresa RiesgoPublished in: J. Syst. Archit. (2010)
Keyphrases
- functional units
- low cost
- vlsi implementation
- reconfigurable hardware
- analog vlsi
- high bandwidth
- management system
- systolic array
- high speed
- hardware implementation
- network structure
- network architecture
- host computer
- level parallelism
- network on chip
- real time
- software architecture
- social networks
- interconnection networks
- reconfigurable architecture
- nm technology
- hardware software
- fine grain
- memory access
- high density
- hardware and software
- power consumption