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Javier Mora
ORCID
Publication Activity (10 Years)
Years Active: 2011-2019
Publications (10 Years): 5
Top Topics
Image Filters
Systolic Array
Highly Flexible
Evolvable Hardware
Top Venues
FPL
ReConFig
DASIP
FCCM
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Publications
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Javier Mora
,
Rubén Salvador
,
Eduardo de la Torre
On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming.
Genet. Program. Evolvable Mach.
20 (2) (2019)
Rafael Zamacola
,
Alberto García-Martínez
,
Javier Mora
,
Andrés Otero
,
Eduardo de la Torre
Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems.
FCCM
(2019)
Rafael Zamacola
,
Alberto García-Martínez
,
Javier Mora
,
Andrés Otero
,
Eduardo de la Torre
IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado.
ReConFig
(2018)
Javier Mora
,
Eduardo de la Torre
Accelerating the evolution of a systolic array-based evolvable hardware system.
Microprocess. Microsystems
56 (2018)
Javier Mora
,
Andrés Otero
,
Eduardo de la Torre
,
Teresa Riesgo
Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs.
ReCoSoC
(2015)
Angel Gallego
,
Javier Mora
,
Andrés Otero
,
Eduardo de la Torre
,
Teresa Riesgo
A scalable evolvable hardware processing array.
ReConFig
(2013)
Angel Gallego
,
Javier Mora
,
Andrés Otero
,
Blanca Lopez
,
Eduardo de la Torre
,
Teresa Riesgo
A self-adaptive image processing application based on evolvable and scalable hardware.
FPL
(2013)
Rubén Salvador
,
Andrés Otero
,
Javier Mora
,
Eduardo de la Torre
,
Teresa Riesgo
,
Lukás Sekanina
Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing.
IEEE Trans. Computers
62 (8) (2013)
Javier Mora
,
Angel Gallego
,
Andrés Otero
,
Eduardo de la Torre
,
Teresa Riesgo
Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform.
DASIP
(2013)
Javier Mora
,
Angel Gallego
,
Andrés Otero
,
Blanca Lopez
,
Eduardo de la Torre
,
Teresa Riesgo
A noise-agnostic self-adaptive image processing application based on evolvable hardware.
DASIP
(2013)
Angel Gallego
,
Javier Mora
,
Andrés Otero
,
Rubén Salvador
,
Eduardo de la Torre
,
Teresa Riesgo
A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays.
IPDPS Workshops
(2013)
Rubén Salvador
,
Andrés Otero
,
Javier Mora
,
Eduardo de la Torre
,
Teresa Riesgo
,
Lukás Sekanina
Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration.
FPL
(2012)
Andrés Otero
,
Rubén Salvador
,
Javier Mora
,
Eduardo de la Torre
,
Teresa Riesgo
,
Lukás Sekanina
A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems.
AHS
(2011)
Rubén Salvador
,
Andrés Otero
,
Javier Mora
,
Eduardo de la Torre
,
Teresa Riesgo
,
Lukás Sekanina
Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support.
AHS
(2011)
Rubén Salvador
,
Andrés Otero
,
Javier Mora
,
Eduardo de la Torre
,
Lukás Sekanina
,
Teresa Riesgo
Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems.
ReConFig
(2011)