René Cumplido

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 25

Top Topics

Frequent Itemsets Mining

Hardware Architecture

Top Venues

Comput. Electr. Eng.

Microprocess. Microsystems

Expert Syst. Appl.

Publications

Martín Letras, Alicia Morales-Reyes, René Cumplido, María-Guadalupe Martínez-Peñaloza, Claudia Feregrino Uribe
A novel partition strategy for efficient implementation of 3D Cellular Genetic Algorithms. Microprocess. Microsystems 104 (2024)
Alejandro Peñuelas-Angulo, Claudia Feregrino Uribe, René Cumplido
An adaptive method for prevention of overflow in reversible data hiding schemes. Expert Syst. Appl. 230 (2023)
G. Melendez-Melendez, Alicia Morales-Reyes, René Cumplido
An adaptive pixel value ordering based reversible data hiding scheme for images. Expert Syst. Appl. 232 (2023)
A. Hernández-Joaquín, G. Melendez-Melendez, René Cumplido
A secure DWT-based dual watermarking scheme for image authentication and copyright protection. Multim. Tools Appl. 82 (27) (2023)
Lázaro Bustio-Martínez, Miguel Ángel Álvarez Carmona, Vitali Herrera-Semenets, Claudia Feregrino Uribe, René Cumplido
A lightweight data representation for phishing URLs detection in IoT environments. Inf. Sci. 603 (2022)
G. Melendez-Melendez, René Cumplido
Reversible Image Authentication Scheme with Tampering Reconstruction Based on Very Deep Super Resolution Network. MICAI (1) (2022)
Lázaro Bustio-Martínez, René Cumplido, Martín Letras, Raudel Hernández-León, Claudia Feregrino Uribe, José Hernández Palancar
FPGA/GPU-based Acceleration for Frequent Itemsets Mining: A Comprehensive Review. ACM Comput. Surv. 54 (9) (2022)
Jorge Echavarria, Alicia Morales-Reyes, René Cumplido, Miguel A. Salido, Claudia Feregrino Uribe
IP-cores watermarking scheme at behavioral level using genetic algorithms. Eng. Appl. Artif. Intell. 104 (2021)
Miguel Morales-Sandoval, Luis Armando Rodriguez Flores, René Cumplido, Jose Juan Garcia-Hernandez, Claudia Feregrino, Ignacio Algredo-Badillo
A Compact FPGA-Based Accelerator for Curve-Based Cryptography in Wireless Sensor Networks. J. Sensors 2021 (2021)
Martín Letras, Lázaro Bustio-Martínez, René Cumplido, Raudel Hernández-León, Claudia Feregrino Uribe
On the design of hardware architectures for parallel frequent itemsets mining. Expert Syst. Appl. 157 (2020)
Lázaro Bustio-Martínez, Mauro Martín Letras Luna, René Cumplido, Raudel Hernández-León, Claudia Feregrino Uribe, José Manuel Bande Serrano
Using hashing and lexicographic order for Frequent Itemsets Mining on data streams. J. Parallel Distributed Comput. 125 (2019)
Ernesto Aparicio-Díaz, René Cumplido, Lázaro Bustio-Martínez, Claudia Feregrino Uribe
Detection And Localization Of Splicing Attacks On Videos Using Block Correlation. PACRIM (2019)
Ernesto Aparicio-Díaz, René Cumplido, Maikel L. Pérez Gort, Claudia Feregrino Uribe
Temporal Copy-Move Forgery Detection and Localization Using Block Correlation Matrix. J. Intell. Fuzzy Syst. 36 (5) (2019)
René Cumplido, Maya B. Gokhale, Claudia Feregrino, Michael Hübner
Guest Editorial: Special Issue on Reconfigurable Computing and FPGA Technology. J. Parallel Distributed Comput. 133 (2019)
Lázaro Bustio-Martínez, Alfredo Muñoz-Briseño, René Cumplido, Raudel Hernández-León, Claudia Feregrino Uribe
A novel multi-core algorithm for frequent itemsets mining in data streams. Pattern Recognit. Lett. 125 (2019)
Lázaro Bustio-Martínez, René Cumplido, Raudel Hernández-León, José Manuel Bande Serrano, Claudia Feregrino Uribe
On the design of hardware-software architectures for frequent itemsets mining on data streams. J. Intell. Inf. Syst. 50 (3) (2018)
Eduardo Cuevas-Farfan, Miguel Morales-Sandoval, René Cumplido
An FPGA-based programmable processor for bilinear pairings. IACR Cryptol. ePrint Arch. 2018 (2018)
Lázaro Bustio-Martínez, René Cumplido, Mauro Martín Letras Luna, Claudia Feregrino Uribe, Raudel Hernández-León, José Manuel Bande Serrano
Approximate frequent itemsets mining on data streams using hashing and lexicographie order in hardware. LASCAS (2017)
Luis Armando Rodriguez Flores, Miguel Morales-Sandoval, René Cumplido, Claudia Feregrino Uribe, Ignacio Algredo-Badillo
A compact FPGA-based microcoded coprocessor for exponentiation in asymmetric encryption. LASCAS (2017)
Roberto de Lima, José Martínez-Carranza, Alicia Morales-Reyes, René Cumplido
Improving the construction of ORB through FPGA-based acceleration. Mach. Vis. Appl. 28 (5-6) (2017)
René Cumplido, Peter Athanas, Eduardo de la Torre
Introduction to the Special Section on FPGAs Technology and Applications. Comput. Electr. Eng. 49 (2016)
Martín Letras, Alicia Morales-Reyes, René Cumplido
A scalable and customizable processor array for implementing cellular genetic algorithms. Neurocomputing 175 (2016)
Juan Andrés Pérez-Celis, José Martínez-Carranza, Alicia Morales-Reyes, Claudia Feregrino Uribe, René Cumplido
An FPGA Architecture to Accelerate the Burrows Wheeler Transform by Using a Linear Sorter. IPDPS Workshops (2016)
René Cumplido, Michael Hübner, Michael J. Wirthlin
Introduction to the special section on FPGAs Technology and Applications. Comput. Electr. Eng. 55 (2016)
Martín Letras, Raudel Hernández-León, René Cumplido
Hardware Architectures for Frequent Itemset Mining Based on Equivalence Classes Partitioning. IPDPS Workshops (2016)
Vladimir Rodríguez-Diez, José Francisco Martínez Trinidad, Jesús Ariel Carrasco-Ochoa, Manuel Lazo-Cortés, Claudia Feregrino Uribe, René Cumplido
A fast hardware software platform for computing irreducible testors. Expert Syst. Appl. 42 (24) (2015)
René Cumplido, Eduardo de la Torre, Claudia Feregrino Uribe, Michael J. Wirthlin
Introduction to Special issue on Reconfigurable computing and FPGAs. Microprocess. Microsystems 39 (7) (2015)
Roberto de Lima, José Martínez-Carranza, Alicia Morales-Reyes, René Cumplido
Accelerating the construction of BRIEF descriptors using an FPGA-based architecture. ReConFig (2015)
Roberto Perez-Andrade, César Torres-Huitzil, René Cumplido
Processor arrays generation for matrix algorithms used in embedded platforms implemented on FPGAs. Microprocess. Microsystems 39 (7) (2015)
Maya B. Gokhale, Michael Hübner, René Cumplido
Message from chairs. ReConFig (2015)
Marisol Rodriguez-Perez, Alicia Morales-Reyes, René Cumplido, Claudia Feregrino Uribe
An analysis of computational models for accelerating the subtractive pixel adjacency model computation. Comput. Electr. Eng. 43 (2015)
Lázaro Bustio, René Cumplido, Raudel Hernández-León, José Manuel Bande Serrano, Claudia Feregrino
Frequent Itemsets Mining in Data Streams Using Reconfigurable Hardware. NFMCP (2015)
Alicia Morales-Reyes, Hugo Jair Escalante, Martín Letras, René Cumplido
An Empirical Analysis on Dimensionality in Cellular Genetic Algorithms. GECCO (2015)
Peter M. Athanas, René Cumplido, Claudia Feregrino Uribe, Eduardo de la Torre
Introduction to Special issue on FPGA Devices and Applications. Microprocess. Microsystems 38 (8) (2014)
Jorge Echavarria, Alicia Morales-Reyes, René Cumplido, Miguel A. Salido
FSM merging and reduction for IP cores watermarking using Genetic Algorithms. ReConFig (2014)
Rommel García, Ignacio Algredo-Badillo, Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido
A compact FPGA-based processor for the Secure Hash Algorithm SHA-256. Comput. Electr. Eng. 40 (1) (2014)
Peter Athanas, René Cumplido, Eduardo de la Torre
Introduction to the special issue on FPGA Technology and Applications. Comput. Electr. Eng. 40 (4) (2014)
José Manuel Bande Serrano, José Hernández Palancar, René Cumplido
The Evaluation of Ordered Features for SMS Spam Filtering. CIARP (2014)
Tomás Balderas-Contreras, René Cumplido, Gustavo Rodríguez Gómez
Synthesizing VHDL from Activity Models in UML 2. Int. J. Circuit Theory Appl. 42 (5) (2014)
Claudia Feregrino Uribe, Ernesto Aparicio-Díaz, José Juan García-Hernández, Alejandra Menendez-Ortiz, René Cumplido, Alicia Morales-Reyes
Hardware architecture for security improved Fallahpour audio watermarking scheme. IEICE Electron. Express 11 (9) (2014)
Vladimir Rodriguez, José F. Martínez, Jesús Ariel Carrasco-Ochoa, Manuel Sabino Lazo-Cortés, René Cumplido, Claudia Feregrino Uribe
A hardware architecture for filtering irreducible testors. ReConFig (2014)
Roberto Perez-Andrade, César Torres-Huitzil, René Cumplido, Juan M. Campos
Processor arrays generation for matrix algorithms used in embedded platforms. ReConFig (2013)
José Manuel Bande Serrano, José Hernández Palancar, René Cumplido
Multi-character cost-effective and high throughput architecture for content scanning. Microprocess. Microsystems 37 (8-D) (2013)
Miguel Morales-Sandoval, Claudia Feregrino Uribe, Paraskevas Kitsos, René Cumplido
)GF(2m) Montgomery multiplier based on LFSR. Comput. Electr. Eng. 39 (2) (2013)
René Cumplido, Peter Athanas, Jürgen Becker
Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011). Int. J. Reconfigurable Comput. 2013 (2013)
Eduardo Cuevas-Farfan, Miguel Morales-Sandoval, René Cumplido, Claudia Feregrino Uribe, Ignacio Algredo-Badillo
A programmable FPGA-based cryptoprocessor for bilinear pairings over F2m. ReCoSoC (2013)
Juan M. Campos, René Cumplido, Claudia Feregrino Uribe, Roberto Perez-Andrade
A parallelization methodology for reconfigurable systems applied to edge detection. ReCoSoC (2013)
Jose Juan Garcia-Hernandez, Ramón Parra-Michel, Claudia Feregrino Uribe, René Cumplido
High payload data-hiding in audio signals based on a modified OFDM approach. Expert Syst. Appl. 40 (8) (2013)
José Manuel Bande Serrano, José Hernández Palancar, René Cumplido
High Throughput Signature Based Platform for Network Intrusion Detection. CIARP (2) (2013)
Diana Goehringer, René Cumplido
Introduction to the special section on 19th reconfigurable architectures workshop (RAW 2012). ACM Trans. Reconfigurable Technol. Syst. 6 (2) (2013)
Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval
FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256. Microprocess. Microsystems 37 (6-7) (2013)
Roberto Perez-Andrade, César Torres-Huitzil, René Cumplido, Juan M. Campos
On an external memory scheme for processor arrays. IEICE Electron. Express 10 (14) (2013)
Jürgen Becker, Ramachandran Vaidyanathan, Peter Athanas, Marco D. Santambrogio, René Cumplido, Oliver Sander
RAW Introduction. IPDPS Workshops (2013)
Francisco Aguirre-Ramos, Claudia Feregrino Uribe, René Cumplido
Video Error Concealment Based on Data Hiding for the Emerging Video Technologies. PSIVT (2013)
Jürgen Becker, Jinian Bian, Christophe Bobda, René Cumplido, Michael Hübner
RAW Introduction. IPDPS Workshops (2012)
Pedro Aaron Hernandez-Avalos, Claudia Feregrino Uribe, René Cumplido
Watermarking using similarities based on fractal codification. Digit. Signal Process. 22 (2) (2012)
Fernando Martin del Campo, Alicia Morales-Reyes, Roberto Perez-Andrade, René Cumplido, Aldo G. Orozco-Lugo, Claudia Feregrino
A multi-cycle fixed point square root module for FPGAs. IEICE Electron. Express 9 (11) (2012)
Ignacio Algredo-Badillo, Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido
Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm. ISVLSI (2012)
Alejandro Rojas, René Cumplido, Jesús Ariel Carrasco-Ochoa, Claudia Feregrino, José Francisco Martínez Trinidad
Hardware-software platform for computing irreducible testors. Expert Syst. Appl. 39 (2) (2012)
Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval
Novel Hardware Architecture for Implementing the Inner Loop of the SHA-2 Algorithms. DSD (2011)
Jose Juan Garcia-Hernandez, Claudia Feregrino Uribe, René Cumplido, Carolina Reta
On the Implementation of a Hardware Architecture for an Audio Data Hiding System. J. Signal Process. Syst. 64 (3) (2011)
Jürgen Becker, Pascal Benoit, René Cumplido
RAW Introduction. IPDPS Workshops (2011)
René Cumplido, Claudia Feregrino Uribe, Jose Juan Garcia-Hernandez
Invited paper: Implementing digital data hiding algorithms in reconfigurable hardware - Experiences on teaching and research. ReCoSoC (2011)
Roberto Perez-Andrade, César Torres-Huitzil, René Cumplido, Juan M. Campos
On a Hybrid and General Control Scheme for Algorithms Represented as a Polytope. IPDPS Workshops (2011)
Santos López-Estrada, René Cumplido
Hardware architecture for adaptive filtering based on energy-CFAR processor for radar target detection. IEICE Electron. Express 7 (9) (2010)
Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido, Ignacio Algredo-Badillo
A Single Formula and its Implementation in FPGA for Elliptic Curve Point Addition Using Affine Representation. J. Circuits Syst. Comput. 19 (2) (2010)
Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval
Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11i standard. Comput. Electr. Eng. 36 (3) (2010)
René Cumplido, Juan M. Campos, Claudia Feregrino Uribe, Jose Roberto Perez-Andrade
Towards a reconfigurable hardware architecture for implementing a LDPC module suitable for software radio systems. Dynamically Reconfigurable Architectures (2010)
Roberto Perez-Andrade, René Cumplido, Claudia Feregrino Uribe, Fernando Martin del Campo
A versatile hardware architecture for a constant false alarm rate processor based on a linear insertion sorter. Digit. Signal Process. 20 (6) (2010)
Tomás Balderas-Contreras, Gustavo Rodríguez Gómez, René Cumplido
A UML 2.0 Profile to Model Block Cipher Algorithms. ECMFA (2010)
Jose Juan Garcia-Hernandez, Claudia Feregrino Uribe, René Cumplido, Ramón Parra-Michel
Improving the security of Fallahpour's audio watermarking scheme. IEICE Electron. Express 7 (14) (2010)
Alejandro Mesa, Claudia Feregrino Uribe, René Cumplido, José Hernández Palancar
A Highly Parallel Algorithm for Frequent Itemset Mining. MCPR (2010)
Lázaro Bustio-Martínez, René Cumplido, José Hernández Palancar, Claudia Feregrino Uribe
On the Design of a Hardware-Software Architecture for Acceleration of SVM's Training Phase. MCPR (2010)
Fernando Martin del Campo, René Cumplido, Roberto Perez-Andrade, Aldo G. Orozco-Lugo
A System on a Programmable Chip Architecture for Data-Dependent Superimposed Training Channel Estimation. Int. J. Reconfigurable Comput. 2009 (2009)
Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido, Ignacio Algredo-Badillo
) multiplier architecture for elliptic curve cryptography. Comput. Electr. Eng. 35 (1) (2009)
Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido, Ignacio Algredo-Badillo
A Run Time Reconfigurable Co-processor for Elliptic Curve Scalar Multiplication. ENC (2009)
Jose Juan Garcia-Hernandez, Carolina Reta, René Cumplido, Claudia Feregrino Uribe
Efficient implementation of the RDM-QIM algorithm in an FPGA. IEICE Electron. Express 6 (14) (2009)
Santos López-Estrada, René Cumplido
FPGA-architecture for Knowledge-Based Target Detection in Radar Signal Processing. ERSA (2009)
Roberto Perez-Andrade, René Cumplido, Claudia Feregrino Uribe, Fernando Martin del Campo
A versatile linear insertion sorter based on an FIFO scheme. Microelectron. J. 40 (12) (2009)
Jose Juan Garcia-Hernandez, Claudia Feregrino Uribe, René Cumplido
FPGA Implementation of a Modulated Complex Lapped Transform for Watermarking Systems. ReConFig (2008)
Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval
Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description. IEICE Trans. Inf. Syst. (10) (2008)
Fernando Martin del Campo, René Cumplido, Roberto Perez-Andrade, Aldo G. Orozco-Lugo
Hybrid Architecture for Data-Dependent Superimposed Training in Digital Receivers. ReConFig (2008)
Zobeida Jezabel Guzman-Zavaleta, Claudia Feregrino Uribe, René Cumplido
A Reversible Data Hiding Algorithm for Radiological Medical Images and Its Hardware Implementation. ReConFig (2008)
Roberto Perez-Andrade, René Cumplido, Claudia Feregrino Uribe, Fernando Martin del Campo
A versatile hardware architecture for a CFAR detector based on a linear insertion sorter. FPL (2008)
Edgar Gomez-Hernández, Claudia Feregrino Uribe, René Cumplido
FPGA Hardware Architecture of the Steganographic ConText Technique. CONIELECOMP (2008)
Tomás Balderas-Contreras, René Cumplido, Claudia Feregrino Uribe
On the design and implementation of a RISC processor extension for the KASUMI encryption algorithm. Comput. Electr. Eng. 34 (6) (2008)
Roberto Perez-Andrade, René Cumplido, Fernando Martin del Campo, Claudia Feregrino Uribe
A Versatile Linear Insertion Sorter Based on a FIFO Scheme. ISVLSI (2008)
Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval
FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks. ReConFig (2008)
Alejandro Rojas, René Cumplido, Jesús Ariel Carrasco-Ochoa, Claudia Feregrino Uribe, José Francisco Martínez Trinidad
FPGA-Based Architecture for Computing Testors. IDEAL (2007)
René Cumplido, Jesús Ariel Carrasco-Ochoa, Claudia Feregrino
On the Design and Implementation of a High Performance Configurable Architecture for Testor Identification. CIARP (2006)
Santos López-Estrada, René Cumplido
Decision Tree Based FPGA-Architecture for Texture Sea State Classification. ReConFig (2006)
Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido
Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture. ICCSA (3) (2006)
René Cumplido, Simon R. Jones, Roger Goodall, Stephen Bateman
A high-performance processor for embedded real-time control. IEEE Trans. Control. Syst. Technol. 13 (3) (2005)
Tomás Balderas-Contreras, René Cumplido
High performance encryption cores for 3G networks. DAC (2005)