Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm.
Ignacio Algredo-BadilloMiguel Morales-SandovalClaudia Feregrino UribeRené CumplidoPublished in: ISVLSI (2012)
Keyphrases
- high efficiency
- segmentation algorithm
- learning algorithm
- computational complexity
- detection algorithm
- k means
- probabilistic model
- highly efficient
- matching algorithm
- expectation maximization
- dynamic programming
- preprocessing
- hardware architectures
- worst case
- real time
- image processing algorithms
- search space
- optimal solution
- general purpose
- computational power
- computational efficiency
- tree structure
- simulated annealing
- computational cost
- neural network