Ignacio Algredo-Badillo

Publication Activity (10 Years)

Years Active: 2006-2023
Publications (10 Years): 17

Top Topics

Hardware Architecture

Top Venues

J. Intell. Fuzzy Syst.

IEICE Trans. Inf. Syst.

Comput. Electron. Agric.

Publications

Monserrat Vázquez-Hernández, Ignacio Algredo-Badillo, Luis Alberto Morales-Rosales, Luis Villaseñor Pineda
White-Box Adversarial Attacks Against Sentiment-Analysis Models using an Aspect-Based Approach. CISETC (2023)
Alan Torres-Alvarado, Luis Alberto Morales-Rosales, Ignacio Algredo-Badillo, Francisco López-Huerta, Mariana Lobato Báez, Juan Carlos López Pimentel
An SHA-3 Hardware Architecture against Failures Based on Hamming Codes and Triple Modular Redundancy. Sensors 22 (8) (2022)
Alan Torres-Alvarado, Luis Alberto Morales-Rosales, Ignacio Algredo-Badillo, Francisco López-Huerta, Mariana Lobato Báez, Juan Carlos López Pimentel
Trade-Off Analysis of Hardware Architectures for Channel-Quality Classification Models. Sensors 22 (7) (2022)
Ignacio Algredo-Badillo, Germàn Portillo-García, Kelsey A. Ramírez-Gutiérrez, Luis Alberto Morales-Rosales
Irregularities recognition system for automotive pieces. Int. J. Comput. Vis. Robotics 12 (6) (2022)
Ignacio Algredo-Badillo, Miguel Morales-Sandoval, Alejandro Medina-Santiago, Carlos Arturo Hernández-Gracidas, Mariana Lobato Báez, Luis Alberto Morales-Rosales
A SHA-256 Hybrid-Redundancy Hardware Architecture for Detecting and Correcting Errors. Sensors 22 (13) (2022)
Alejandro Medina-Santiago, Carlos Arturo Hernández-Gracidas, Luis Alberto Morales-Rosales, Ignacio Algredo-Badillo, Monica Amador García, Jorge Antonio Orozco Torres
CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions. Sensors 21 (21) (2021)
Ignacio Algredo-Badillo, Kelsey A. Ramírez-Gutiérrez, Luis Alberto Morales-Rosales, Daniel Pacheco Bautista, Claudia Feregrino Uribe
Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES. Sensors 21 (16) (2021)
Miguel Morales-Sandoval, Luis Armando Rodriguez Flores, René Cumplido, Jose Juan Garcia-Hernandez, Claudia Feregrino, Ignacio Algredo-Badillo
A Compact FPGA-Based Accelerator for Curve-Based Cryptography in Wireless Sensor Networks. J. Sensors 2021 (2021)
Daniel Pacheco Bautista, Ricardo Carreño Aguilera, Francisco Aguilar Acevedo, Ignacio Algredo-Badillo
Bit-Vector-Based Hardware Accelerator for DNA Alignment Tools. J. Circuits Syst. Comput. 30 (5) (2021)
Luis Alberto Morales-Rosales, Ignacio Algredo-Badillo, Mariana Lobato Báez, Carlos Arturo Hernández-Gracidas, Héctor Rodríguez Rangel
A fuzzy petri net model for assessing analogical reasoning in children ranging from 5 to 8 years old. J. Intell. Fuzzy Syst. 39 (5) (2020)
Juan Carlos Carrillo-Alarcón, Luis Alberto Morales-Rosales, Héctor Rodríguez Rangel, Mariana Lobato Báez, Antonio Muñoz, Ignacio Algredo-Badillo
A Metaheuristic Optimization Approach for Parameter Estimation in Arrhythmia Classification from Unbalanced Data. Sensors 20 (11) (2020)
Ignacio Algredo-Badillo, Luis Alberto Morales-Rosales, Carlos Arturo Hernández-Gracidas, Juan C. Cruz-Victoria, Daniel Pacheco Bautista, Miguel Morales-Sandoval
Real time FPGA-ANN architecture for outdoor obstacle detection focused in road safety. J. Intell. Fuzzy Syst. 36 (5) (2019)
Kelsey A. Ramírez-Gutiérrez, Alejandro Medina-Santiago, Alfonso Martinez Cruz, Ignacio Algredo-Badillo, Hayde Peregrina-Barreto
Eggshell deformation detection applying computer vision. Comput. Electron. Agric. 158 (2019)
Alejandro Medina-Santiago, Mario Alfredo Reyes-Barranca, Ignacio Algredo-Badillo, Alfonso Martinez Cruz, Kelsey A. Ramírez-Gutiérrez, Eleazar Adrián Cortés-Barrón
Reconfigurable arithmetic logic unit designed with threshold logic gates. IET Circuits Devices Syst. 13 (1) (2019)
Luis Alberto Morales-Rosales, Ignacio Algredo-Badillo, Carlos Arturo Hernández-Gracidas, Héctor Rodríguez Rangel, Mariana Lobato Báez
On-road obstacle detection video system for traffic accident prevention. J. Intell. Fuzzy Syst. 35 (1) (2018)
Ignacio Algredo-Badillo, Francisco Rubén Castillo Soria, Kelsey A. Ramírez-Gutiérrez, Luis Alberto Morales-Rosales, Alejandro Medina-Santiago, Claudia Feregrino Uribe
Lightweight Security Hardware Architecture Using DWT and AES Algorithms. IEICE Trans. Inf. Syst. (11) (2018)
Luis Armando Rodriguez Flores, Miguel Morales-Sandoval, René Cumplido, Claudia Feregrino Uribe, Ignacio Algredo-Badillo
A compact FPGA-based microcoded coprocessor for exponentiation in asymmetric encryption. LASCAS (2017)
M. A. Saldaña-O., Luis Enrique Ramos Velasco, J. P. Ordaz-O., Abel García-Barrientos, Ignacio Algredo-Badillo, Jean-François Balmat, Frédéric Lafont
A comparative study of the wavenet PID controllers for applications in non-linear systems. CCE (2015)
Rommel García, Ignacio Algredo-Badillo, Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido
A compact FPGA-based processor for the Secure Hash Algorithm SHA-256. Comput. Electr. Eng. 40 (1) (2014)
Eduardo Cuevas-Farfan, Miguel Morales-Sandoval, René Cumplido, Claudia Feregrino Uribe, Ignacio Algredo-Badillo
A programmable FPGA-based cryptoprocessor for bilinear pairings over F2m. ReCoSoC (2013)
Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval
FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256. Microprocess. Microsystems 37 (6-7) (2013)
Francisco Rubén Castillo Soria, Gustavo Fernández Torres, Ignacio Algredo-Badillo
A Lossless Data Hiding Technique based on AES-DWT CoRR (2012)
Ernesto Cortés Pérez, Ignacio Algredo-Badillo, Víctor Hugo García Rodríguez
Performance Analysis of ANFIS in short term Wind Speed Prediction CoRR (2012)
Ignacio Algredo-Badillo, Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido
Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm. ISVLSI (2012)
Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval
Novel Hardware Architecture for Implementing the Inner Loop of the SHA-2 Algorithms. DSD (2011)
Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido, Ignacio Algredo-Badillo
A Single Formula and its Implementation in FPGA for Elliptic Curve Point Addition Using Affine Representation. J. Circuits Syst. Comput. 19 (2) (2010)
Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval
Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11i standard. Comput. Electr. Eng. 36 (3) (2010)
Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido, Ignacio Algredo-Badillo
) multiplier architecture for elliptic curve cryptography. Comput. Electr. Eng. 35 (1) (2009)
Miguel Morales-Sandoval, Claudia Feregrino Uribe, René Cumplido, Ignacio Algredo-Badillo
A Run Time Reconfigurable Co-processor for Elliptic Curve Scalar Multiplication. ENC (2009)
Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval
Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description. IEICE Trans. Inf. Syst. (10) (2008)
Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval
FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks. ReConFig (2008)
Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido
Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture. ICCSA (3) (2006)