Login / Signup
Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES.
Ignacio Algredo-Badillo
Kelsey A. Ramírez-Gutiérrez
Luis Alberto Morales-Rosales
Daniel Pacheco Bautista
Claudia Feregrino Uribe
Published in:
Sensors (2021)
Keyphrases
</>
hardware architecture
error detection and correction
hardware implementation
encryption algorithm
error correction
data transmission
hardware architectures
associative memory
field programmable gate array
real time
metadata
digital libraries
wireless sensor networks
xilinx virtex