A versatile hardware architecture for a constant false alarm rate processor based on a linear insertion sorter.
Roberto Perez-AndradeRené CumplidoClaudia Feregrino UribeFernando Martin del CampoPublished in: Digit. Signal Process. (2010)
Keyphrases
- false alarm rate
- hardware architecture
- detection rate
- processing elements
- false alarms
- xilinx virtex
- target detection
- hardware implementation
- hardware architectures
- field programmable gate array
- detection algorithm
- real time
- associative memory
- false positive rate
- parallel processing
- computer systems
- efficient implementation
- parallel architecture
- support vector machine