A versatile hardware architecture for a CFAR detector based on a linear insertion sorter.
Roberto Perez-AndradeRené CumplidoClaudia Feregrino UribeFernando Martin del CampoPublished in: FPL (2008)
Keyphrases
- hardware architecture
- hardware implementation
- false alarm rate
- hardware architectures
- false alarm probability
- processing elements
- genetic algorithm
- general purpose
- detection algorithm
- associative memory
- case study
- pairwise
- artificial neural networks
- efficient implementation
- false alarms
- field programmable gate array