Jinian Bian

Publication Activity (10 Years)

Years Active: 1997-2023
Publications (10 Years): 1

Top Topics

Hardware Implementation

Merging Algorithm

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

Publications

Kang Zhao, Yuchun Ma, Ruining He, Jixing Zhang, Ning Xu, Jinian Bian
Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow. ACM Trans. Reconfigurable Technol. Syst. 16 (2) (2023)
Jixin Zhang, Ning Xu, Yuchun Ma, Yu Wang, Jinian Bian
Data dependency aware prefetch scheduling for Dynamic Partial reconfigurable designs. ASICON (2013)
Jiliang Zhang, Yaping Lin, Yongqiang Lu, Ray C. C. Cheung, Wenjie Che, Qiang Zhou, Jinian Bian
Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits. FCCM (2013)
Qingyu Liu, Yuchun Ma, Yu Wang, Wayne Luk, Jinian Bian
RALP: Reconvergence-aware layer partitioning for 3D FPGAs. ReConFig (2013)
Ruining He, Guoqiang Liang, Yuchun Ma, Yu Wang, Jinian Bian
Unification of PR Region floorplanning and Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs. J. Circuits Syst. Comput. 22 (4) (2013)
Yuanyuan Li, Ning Xu, Yuchun Ma, Jinian Bian
Incremental 3D NoC synthesis based on physical-aware router merging algorithm. ASICON (2013)
Guoqiang Liang, Yuchun Ma, Kang Zhao, Jinian Bian
Efficient custom instruction generation based on characterizing of basic blocks. CSCWD (2013)
Zhongda Yuan, Yuchun Ma, Jinian Bian, Kang Zhao
Automatic enhanced CDFG generation based on runtime instrumentation. CSCWD (2013)
Jiliang Zhang, Yaping Lin, Yongqiang Lyu, Gang Qu, Ray C. C. Cheung, Wenjie Che, Qiang Zhou, Jinian Bian
FPGA IP protection by binding Finite State Machine to Physical Unclonable Function. FPL (2013)
Kang Zhao, Jinian Bian
Pruning-Based Trace Signal Selection Algorithm for Data Acquisition in Post-Silicon Validation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2012)
Zhongda Yuan, Yuchun Ma, Jinian Bian
SMPP: Generic SAT Solver over Reconfigurable Hardware Accelerator. IPDPS Workshops (2012)
Ruining He, Yuchun Ma, Kang Zhao, Jinian Bian
ISBA: An independent set-based algorithm for automated partial reconfiguration module generation. ICCAD (2012)
Ruining He, Guoqiang Liang, Yuchun Ma, Yu Wang, Jinian Bian
PDPR: Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs. ARC (2012)
Jürgen Becker, Jinian Bian, Christophe Bobda, René Cumplido, Michael Hübner
RAW Introduction. IPDPS Workshops (2012)
Ou He, Sheqin Dong, Wooyoung Jang, Jinian Bian, David Z. Pan
UNISM: Unified Scheduling and Mapping for General Networks on Chip. IEEE Trans. Very Large Scale Integr. Syst. 20 (8) (2012)
Kang Zhao, Jinian Bian
Pruning-based trace signal selection algorithm. ASP-DAC (2011)
Limin Zhu, Jinian Bian, Qiang Zhou, Yici Cai
A fast recursive detailed routing algorithm for hierarchical FPGAs. CSCWD (2011)
Kang Zhao, Jinian Bian
Instruction-level hardware/software partition through DFG exploration. CSCWD (2011)
Kang Zhao, Jinian Bian
Processor Accelerator Customization through Data Flow Graph Exploration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2011)
Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto
Buffer Planning for IP Placement Using Sliced-LFF. VLSI Design 2011 (2011)
Shujun Deng, Kwang-Ting Cheng, Jinian Bian, Zhiqiu Kong
Mutation-based diagnostic test generation for hardware design error diagnosis. ITC (2010)
Junbo Yu, Qiang Zhou, Gang Qu, Jinian Bian
Behavioral level dual-vth design for reduced leakage power with thermal awareness. DATE (2010)
Hui Dai, Qiang Zhou, Jinian Bian
Multilevel Optimization for Large-Scale Hierarchical FPGA Placement. J. Comput. Sci. Technol. 25 (5) (2010)
Kang Zhao, Jinian Bian
Peeling algorithm for custom instruction identification. APCCAS (2010)
Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng
Bus via reduction based on floorplan revising. ACM Great Lakes Symposium on VLSI (2010)
Dawei Liu, Qiang Zhou, Yongqiang Lu, Jinian Bian
A low power clock network placement framework. ISQED (2010)
Wentao Sui, Sheqin Dong, Jinian Bian
Wirelength-driven force-directed 3D FPGA placement. ACM Great Lakes Symposium on VLSI (2010)
Limin Zhu, Qiang Zhou, Yici Cai, Jinian Bian
An architecture-aware routing optimization via satisfiabilty for hierarchical FPGA. CSCWD (2010)
Yanni Zhao, Jinian Bian, Shujun Deng, Zhiqiu Kong
Random stimulus generation with self-tuning. CSCWD (2009)
Yanni Zhao, Jinian Bian, Shujun Deng, Zhiqiu Kong, Kang Zhao
Constrained Stimulus Generation with Self-Adjusting Using Tabu Search with Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Hui Dai, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong
Fast placement for large-scale hierarchical FPGAs. CAD/Graphics (2009)
Junbo Yu, Qiang Zhou, Gang Qu, Jinian Bian
Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto
Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2009)
Dawei Liu, Qiang Zhou, Jinian Bian, Yanming Jia
Global density smoothing technique for analytical placement algorithm. CAD/Graphics (2009)
Dawei Liu, Qiang Zhou, Jinian Bian, Yici Cai, Xianlong Hong
Cell shifting aware of wirelength and overlap. ISQED (2009)
Junbo Yu, Qiang Zhou, Jinian Bian
Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resources. ASP-DAC (2009)
Lixin Cheng, Jinian Bian, Yunyun Liu
An approach to synthesis delay semantics in VHDL. CAD/Graphics (2009)
Shujun Deng, Zhiqiu Kong, Jinian Bian, Yanni Zhao
Self-adjusting constrained random stimulus generation using splitting evenness evaluation and XOR constraints. ASP-DAC (2009)
Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto
Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration. ISQED (2008)
Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto
Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2008)
Kang Zhao, Jinian Bian, Chenqian Jiang, Sheqin Dong, Satoshi Goto
Cache miss reduction through hardware-assisted loop optimization. CSCWD (2008)
Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto
Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2008)
Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng
A novel fixed-outline floorplanner with zero deadspace for hierarchical design. ICCAD (2008)
Xing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong
MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. FPL (2008)
Kun Tong, Jinian Bian, Haili Wang
A cooperative universal data model platform for the data-centric electronic system-level design. Adv. Eng. Informatics 22 (3) (2008)
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian
Low power clock buffer planning methodology in F-D placement for large scale circuit design. ASP-DAC (2008)
Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto
HyMacs: hybrid memory access optimization based on custom-instruction scheduling. ACM Great Lakes Symposium on VLSI (2008)
Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong
An effective buffer planning algorithm for IP based fixed-outline SOC placement. ACM Great Lakes Symposium on VLSI (2007)
Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (4) (2007)
Chenqian Jiang, Jinian Bian, Kang Zhao
Power-driven Real-time System Design with Energy Efficiency via ISA Customization. CAD/Graphics (2007)
Xiaoqing Yang, Jinian Bian, Shujun Deng, Yanni Zhao
EHSAT Modeling from Algorithm Description for RTL Model Checking. ATS (2007)
Hui Zhang, Jinian Bian
A Management System of Metropolis Energy Information. CSCWD (2007)
Shujun Deng, Jinian Bian, Weimin Wu, Xiaoqing Yang, Yanni Zhao
EHSAT: An Efficient RTL Satisfiability Solver Using an Extended DPLL Procedure. DAC (2007)
Yanhua Wang, Qiang Zhou, Jinian Bian, Junhua Qu
VPH: Versatile Routability-Driven Place Algorithm for Hierarchical FPGAs Based on VPR. CAD/Graphics (2007)
Kang Zhao, Jinian Bian, Sheqin Dong
A Fast Custom Instructions Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design. CSCWD (2007)
Zhipeng Liu, Jinian Bian, Qiang Zhou, Hui Dai
Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan. ISVLSI (2007)
Ming Zhu, Jinian Bian, Weimin Wu
A novel collaborative scheme of simulation and model checking for system properties verification. Comput. Ind. 57 (8-9) (2006)
Shujun Deng, Weimin Wu, Jinian Bian
Bounded Model Checking Combining Symbolic Trajectory Evaluation Abstraction with Hybrid Three-Valued SAT Solving. CSCWD (Selected Papers) (2006)
Liang Zhu, Jinian Bian
From Software to Hardware - A Novel TLM Auto-Generating Method. APCCAS (2006)
Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng
Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2006)
Kang Zhao, Jinian Bian
A Clustering ILP Model for Fast Instruction Selection in Embedded Applicated Specific Processor Design. APCCAS (2006)
Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani
Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. ACM Trans. Design Autom. Electr. Syst. 11 (2) (2006)
Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng
Integrating dynamic thermal via planning with 3D floorplanning algorithm. ISPD (2006)
Yawen Niu, Jinian Bian, Haili Wang, Kun Tong
An Efficient Cooperative Design Framework for SOC On-Chip Communication Architecture System-Level Design. CSCWD (Selected Papers) (2006)
Shujun Deng, Weimin Wu, Jinian Bian
Cooperative Bounded Model Checking Using STE and Hybrid Three-Valued SAT Solving. CSCWD (2006)
Yawen Niu, Jinian Bian, Haili Wang, Kun Tong, Liang Zhu
AGOM: A Novel Method of Embedded System Communication Architecture Design in System Level Design. CSCWD (2006)
Zhen Zhao, Jinian Bian, Zhipeng Liu, Yunfeng Wang, Kang Zhao
High Level Synthesis with Multiple supply Voltages for Energy and Combined Peak Power Minimization. APCCAS (2006)
Kun Tong, Jinian Bian, Haili Wang
Universal data model platform: the data-centric evolution for system level codesign. CSCWD (2006)
Kang Zhao, Jinian Bian, Sheqin Dong
A Heterogeneous Dependency Graph as Intermediate Representation for Instruction Set Customization. JCIS (2006)
Qiang Wu, Jinian Bian, Hongxi Xue
System-level architectural exploration using allocation-on-demand technique. ASP-DAC (2005)
Haili Wang, Jinian Bian, Qiang Wu, Yunfeng Wang
iTuCoMe: HCDFG-based incremental tuning HW/SW co-design methodology for multi-level exploration. CSCWD (2) (2005)
Feng Lin, Haili Wang, Jinian Bian
HW/SW Interface Synthesis Based on Avalon Bus Specification for Nios-Oriented SoC Design. FPT (2005)
Jianzhou Zhao, Jinian Bian, Weimin Wu
Cooperation of SMV and Jeda for the property checking of mixed control and data intensive designs. CSCWD (2) (2005)
Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani
A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. ISCAS (6) (2005)
Yunfeng Wang, Jinian Bian, Xianlong Hong, Liu Yang, Qiang Zhou, Qiang Wu
A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design. ICESS (2005)
Yunfeng Wang, Jinian Bian, Xianlong Hong
Interconnect delay optimization via high level re-synthesis after floorplanning. ISCAS (6) (2005)
Haili Wang, Jinian Bian, Yawen Niu, Kun Tong, Yunfeng Wang
CA-Ex: A Tuning-Incremental Methodology for Communication Architectures in Embedded Systems. ICESS (2004)
Ming Zhu, Jinian Bian, Weimin Wu
Model Optimization Techniques in a Verification Platform for Classified Properties. ICESS (2004)
Qiang Wu, Jinian Bian, Hongxi Xue
A Distributed Architecture Model for Heterogeneous Multiprocessor System-on-Chip Design. ICESS (2004)
Jianzhou Zhao, Jinian Bian, Weimin Wu
PFGASAT- A Genetic SAT Solver Combining Partitioning and Fuzzy Strategie. COMPSAC (2004)
Ming Zhu, Jinian Bian, Weimin Wu, Hongxi Xue
Property Classification for Functional Verification Based. Asian Test Symposium (2003)
Chin Ngai Sze, Wangning Long, Yu-Liang Wu, Jinian Bian
Accelerating Logic Rewiring Using Implication Analysis Tree. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Wangning Long, Yu-Liang Wu, Jinian Bian
IBAW: an implication-tree based alternative-wiring logic transformation algorithm. ASP-DAC (2000)
Jinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue, Xianlong Hong
FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking. ASP-DAC (1999)
Jinian Bian, Hongxi Xue, Ming Su
VIDE: a visual VHDL integrated design environment. ASP-DAC (1997)