Hannah Honghua Yang

Publication Activity (10 Years)

Years Active: 1994-2007
Publications (10 Years): 0

Publications

Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (4) (2007)
Hsun-Cheng Lee, Yao-Wen Chang, Hannah Honghua Yang
-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (8) (2007)
Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng
Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2006)
Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani
Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. ACM Trans. Design Autom. Electr. Syst. 11 (2) (2006)
Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng
Integrating dynamic thermal via planning with 3D floorplanning algorithm. ISPD (2006)
Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong
Microarchitecture evaluation with floorplanning and interconnect pipelining. ASP-DAC (2005)
Guowu Yang, Xiaoyu Song, Hannah Honghua Yang, Fei Xie
A Theoretical Upper Bound for IP-Based Floorplanning. COCOON (2005)
Yan Feng, Dinesh P. Mehta, Hannah Honghua Yang
Constrained floorplanning using network flows. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (4) (2004)
Changqi Yang, Xianlong Hong, Hannah Honghua Yang, Qiang Zhou, Yici Cai, Yongqiang Lu
Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration. ISCAS (5) (2004)
Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani
Integrated floorplanning with buffer/channel insertion for bus-based designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (6) (2003)
Yan Feng, Dinesh P. Mehta, Hannah Honghua Yang
Constrained "Modern" Floorplanning. ISPD (2003)
Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hannah Honghua Yang
Multilevel floorplanning/placement for large-scale modules using B*-trees. DAC (2003)
Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs. ISPD (2002)
Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang
On extending slicing floorplan to handle L/T-shaped modules andabutment constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (6) (2001)
Hung-Ming Chen, D. F. Wong, Wai-Kei Mak, Hannah Honghua Yang
Faster and more accurate wiring evaluation in interconnect-centric floorplanning. ACM Great Lakes Symposium on VLSI (2001)
Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang
Slicing floorplans with range constraint. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (2) (2000)
Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani
Integrated floorplanning and interconnect planning. ICCAD (1999)
Jeremy Casas, Hannah Honghua Yang, Manpreet Khaira, Mandar Joshi, Thomas Tetzlaff, Steve W. Otto, Erik Seligman
Logic Verification of Very Large Circuits Using Shark. VLSI Design (1999)
Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang
Slicing floorplans with boundary constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (9) (1999)
Hannah Honghua Yang, Martin D. F. Wong
Optimal min-area min-cut replication in partitioned circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (11) (1998)
Hannah Honghua Yang, Martin D. F. Wong
Circuit clustering for delay minimization under area and pin constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (9) (1997)
Hannah Honghua Yang, Martin D. F. Wong
Balanced partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (12) (1996)
Hannah Honghua Yang, D. F. Wong
New algorithms for min-cut replication in partitioned circuits. ICCAD (1995)
Hannah Honghua Yang, D. F. Wong
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs. ICCAD (1994)