Logic Verification of Very Large Circuits Using Shark.
Jeremy CasasHannah Honghua YangManpreet KhairaMandar JoshiThomas TetzlaffSteve W. OttoErik SeligmanPublished in: VLSI Design (1999)
Keyphrases
- asynchronous circuits
- delay insensitive
- logic synthesis
- logic circuits
- digital circuits
- model checking
- chip design
- verification method
- bounded model checking
- model checker
- formal verification
- floating gate
- low power
- modal logic
- high speed
- shift register
- tunnel diode
- linear time temporal logic
- real time
- quantum computing
- predicate logic
- signature verification
- classical logic
- finite state machines
- temporal logic
- multi agent systems