Xianlong Hong

Publication Activity (10 Years)

Years Active: 1992-2011
Publications (10 Years): 0

Publications

Kan Wang, Sheqin Dong, Yuchun Ma, Yu Wang, Xianlong Hong, Jason Cong
Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2011)
Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong
Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs. ASP-DAC (2011)
Yuchun Ma, Qiang Zhou, Pingqiang Zhou, Xianlong Hong
Thermal Impacts of Leakage Power in 2D/3D floorplanning. J. Circuits Syst. Comput. 19 (7) (2010)
Shan Zeng, Wenjian Yu, Xianlong Hong, Chung-Kuan Cheng
Efficient Power Network Analysis with Modeling of Inductive Effects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2010)
Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong
PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization. ASP-DAC (2010)
Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta, Xianlong Hong
Effective congestion reduction for IC package substrate routing. ACM Trans. Design Autom. Electr. Syst. 15 (3) (2010)
Shenghua Liu, Yuchun Ma, Xianlong Hong, Yu Wang
Simultaneous slack budgeting and retiming for synchronous circuits optimization. ASP-DAC (2010)
Yin Shen, Qiang Zhou, Yici Cai, Xianlong Hong
ECP- and CMP-Aware Detailed Routing Algorithm for DFM. IEEE Trans. Very Large Scale Integr. Syst. 18 (1) (2010)
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement. IEEE Trans. Very Large Scale Integr. Syst. 18 (12) (2010)
Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong
Substrate Topological Routing for High-Density Packages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (2) (2009)
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu
A single layer zero skew clock routing in X architecture. Sci. China Ser. F Inf. Sci. 52 (8) (2009)
Ruijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. ASP-DAC (2009)
Shan Zeng, Wenjian Yu, Jin Shi, Xianlong Hong, Chung-Kuan Cheng
Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2009)
Xiaoyi Wang, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Jacob Relles
An efficient decoupling capacitance optimization using piecewise polynomial models. DATE (2009)
Yuchun Ma, Xin Li, Yu Wang, Xianlong Hong
Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Hui Dai, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong
Fast placement for large-scale hierarchical FPGAs. CAD/Graphics (2009)
Xu He, Sheqin Dong, Xianlong Hong, Satoshi Goto
Integrated interlayer via planning and pin assignment for 3D ICs. SLIP (2009)
Fubing Mao, Yuchun Ma, Ning Xu, Xianlong Hong, Yu Wang
Multi-objective Floorplanning Based on Fuzzy Logic. FSKD (4) (2009)
Shan Zeng, Wenjian Yu, Wanping Zhang, Jian Wang, Xianlong Hong, Chung-Kuan Cheng
Efficient power network analysis with complete inductive modeling. ISQED (2009)
Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta, Xianlong Hong
Diffusion-driven congestion reduction for substrate topological routing. ISPD (2009)
Xin Li, Yuchun Ma, Xianlong Hong
A novel thermal optimization flow using incremental floorplanning for 3D ICs. ASP-DAC (2009)
Qiang Zhou, Xin Zhao, Yici Cai, Xianlong Hong
An MTCMOS technology for low-power physical design. Integr. 42 (3) (2009)
Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong
Modern Floorplanning with Boundary Clustering Constraint. ISVLSI (2009)
Sheqin Dong, Hongjie Bai, Xianlong Hong, Satoshi Goto
Buffer Planning for 3D ICs. ISCAS (2009)
Dawei Liu, Qiang Zhou, Jinian Bian, Yici Cai, Xianlong Hong
Cell shifting aware of wirelength and overlap. ISQED (2009)
Haixia Yan, Qiang Zhou, Xianlong Hong
Thermal aware placement in 3D ICs using quadratic uniformity modeling approach. Integr. 42 (2) (2009)
Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong
Simultaneous buffer and interlayer via planning for 3D floorplanning. ISQED (2009)
Yuchun Ma, Xiang Qiu, Xiangqing He, Xianlong Hong
Incremental power optimization for multiple supply voltage design. ISQED (2009)
Xiang Qiu, Yuchun Ma, Xiangqing He, Xianlong Hong
IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization. ISQED (2008)
Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. ASP-DAC (2008)
Yanming Jia, Yici Cai, Xianlong Hong
Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Changdao Dong, Qiang Zhou, Yici Cai, Xianlong Hong
Wire density driven top-down global placement for CMP variation control. APCCAS (2008)
Weixiang Shen, Yici Cai, Xianlong Hong
Leakage power optimization for clock network using dual-Vth technology. ISCAS (2008)
Shuai Li, Jin Shi, Yici Cai, Xianlong Hong
Vertical via design techniques for multi-layered P/G networks. ASP-DAC (2008)
Yici Cai, Jin Shi, Zhu Pan, Xianlong Hong, Sheldon X.-D. Tan
Large scale P/G grid transient simulation using hierarchical relaxed approach. Integr. 41 (1) (2008)
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu
Zero skew clock routing in X-architecture based on an improved greedy matching algorithm. Integr. 41 (3) (2008)
Liangpeng Guo, Yici Cai, Qiang Zhou, Le Kang, Xianlong Hong
A novel performance driven power gating based on distributed sleep transistor network. ACM Great Lakes Symposium on VLSI (2008)
Yanming Jia, Yici Cai, Xianlong Hong
Full-chip routing system for reducing Cu CMP & ECP variation. SBCCI (2008)
Ning Mi, Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
Statistical Analysis of On-Chip Power Delivery Networks Considering Lognormal Leakage Current Variations With Spatial Correlation. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2008)
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
Activity and register placement aware gated clock network design. ISPD (2008)
Yibo Wang, Yici Cai, Xianlong Hong
A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation. ISVLSI (2008)
Yici Cai, Qiang Zhou, Xianlong Hong, Rui Shi, Yang Wang
Application of optical proximity correction technology. Sci. China Ser. F Inf. Sci. 51 (2) (2008)
Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto
Symmetry constraint based on mismatch analysis for analog layout in SOI technology. ASP-DAC (2008)
Tom Tong Jing, Yu Hu, Zhe Feng, Xianlong Hong, Xiaodong Hu, Guiying Yan
A full-scale solution to the rectilinear obstacle-avoiding Steiner problem. Integr. 41 (3) (2008)
Yici Cai, Le Kang, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan
Random Walk Guided Decap Embedding for Power/Ground Network Optimization. IEEE Trans. Circuits Syst. II Express Briefs (1) (2008)
Yin Shen, Yici Cai, Qiang Zhou, Xianlong Hong
DFM Based Detailed Routing Algorithm for ECP and CMP. ISQED (2008)
Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong
Topological routing to maximize routability for package substrate. DAC (2008)
Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (11) (2008)
Hailong Yao, Subarna Sinha, Jingyu Xu, Charles C. Chiang, Yici Cai, Xianlong Hong
Efficient range pattern matching algorithm for process-hotspot detection. IET Circuits Devices Syst. 2 (1) (2008)
Haixia Yan, Qiang Zhou, Xianlong Hong
Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm. ISQED (2008)
Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong
Early Stage Power Supply Planning: A Heuristic Method for Codesign of Power/Ground Network and Floorplan. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Zhe Feng, Lei He, Xianlong Hong
Fashion: A Fast and Accurate Solution to Global Routing Problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (4) (2008)
Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong
Heuristic power/ground network and floorplan co-design method. ASP-DAC (2008)
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
Low Power Gated Clock Tree Driven Placement. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2008)
Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong
Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (8) (2008)
Xing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong
MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. FPL (2008)
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
Gate planning during placement for gated clock network. ICCD (2008)
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian
Low power clock buffer planning methodology in F-D placement for large scale circuit design. ASP-DAC (2008)
Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong Hong
New timing and routability driven placement algorithms for FPGA synthesis. ACM Great Lakes Symposium on VLSI (2007)
Xinjie Wei, Yici Cai, Xianlong Hong
Effective Acceleration of Iterative Slack Distribution Process. ISCAS (2007)
Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong
An effective buffer planning algorithm for IP based fixed-outline SOC placement. ACM Great Lakes Symposium on VLSI (2007)
Lingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma
A Fast 3D-BSG Algorithm for 3D Packing Problem. ISCAS (2007)
Ning Mi, Sheldon X.-D. Tan, Pu Liu, Jian Cui, Yici Cai, Xianlong Hong
Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks. ICCAD (2007)
Yibo Wang, Yici Cai, Xianlong Hong, Yi Zou
Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2007)
Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, Xianlong Hong
DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. ASP-DAC (2007)
Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. ICCAD (2007)
Yanming Jia, Yici Cai, Xianlong Hong
Dummy fill aware buffer insertion during routing. ACM Great Lakes Symposium on VLSI (2007)
Hailong Yao, Yici Cai, Xianlong Hong
CMP-aware Maze Routing Algorithm for Yield Enhancement. ISVLSI (2007)
Yaoguang Wei, Sheqin Dong, Xianlong Hong
APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement. Integr. 40 (4) (2007)
Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (4) (2007)
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. ISVLSI (2007)
Xinjie Wei, Yici Cai, Xianlong Hong
Physical aware clock skew rescheduling. ACM Great Lakes Symposium on VLSI (2007)
Yongqiang Lu, Xianlong Hong, Qiang Zhou, Yici Cai, Jun Gu
An efficient quadratic placement based on search space traversing technology. Integr. 40 (3) (2007)
Yanfeng Wang, Qiang Zhou, Xianlong Hong, Yici Cai
Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building. ISCAS (2007)
Jin Shi, Yici Cai, Sheldon X.-D. Tan, Jeffrey Fan, Xianlong Hong
Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (4) (2007)
Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong
Voltage Island Generation in Cell Based Dual-Vdd Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2007)
Qiang Zhou, Yici Cai, Duo Li, Xianlong Hong
A Yield-Driven Gridless Router. J. Comput. Sci. Technol. 22 (5) (2007)
Haixia Yan, Zhuoyuan Li, Xianlong Hong, Qiang Zhou
Unified Quadratic Programming Approach For 3-D Mixed Mode Placement. ISCAS (2007)
Tom Tong Jing, Zhe Feng, Yu Hu, Xianlong Hong, Xiaodong Hu, Guiying Yan
lambda-OAT: lambda-Geometry Obstacle-Avoiding Tree Construction With O(nlog n) Complexity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (11) (2007)
Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan, Le Kang
Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos. ASP-DAC (2007)
Le Kang, Yici Cai, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan, Xiaoyi Wang
Simultaneous Switching Noise Consideration for Power/Ground Network Optimization. CAD/Graphics (2007)
Le Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan
Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach. ASP-DAC (2007)
Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong
Interconnect Power Optimization Based on Timing Analysis. ISVLSI (2007)
Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
Statistical model order reduction for interconnect circuits considering spatial correlations. DATE (2007)
Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong
Logic and Layout Aware Voltage Island Generation for Low Power Design. ASP-DAC (2007)
Yaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma
An accurate and efficient probabilistic congestion estimation model in x architecture. SLIP (2007)
Pingqiang Zhou, Yuchun Ma, Qiang Zhou, Xianlong Hong
Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning. CAD/Graphics (2007)
Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. ASP-DAC (2007)
Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong
Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation. ASP-DAC (2007)
Yici Cai, Bin Liu, Jin Shi, Qiang Zhou, Xianlong Hong
Power Delivery Aware Floorplanning for Voltage Island Designs. ISQED (2007)
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu
Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture. ISQED (2007)
Hongjie Bai, Sheqin Dong, Xianlong Hong
Congestion Driven Buffer Planning for X-Architecture. ISQED (2007)
Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
Partitioning-based decoupling capacitor budgeting via sequence of linear programming. Integr. 40 (4) (2007)
Yu Hu, Tong Jing, Zhe Feng, Xianlong Hong, Xiaodong Hu, Guiying Yan
ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm. J. Comput. Sci. Technol. 21 (1) (2006)
Jingyu Xu, Xianlong Hong, Tong Jing, Yang Yang
Obstacle-avoiding rectilinear minimum-delay Steiner tree construction toward IP-block-based SOC design. IEEE Trans. Circuits Syst. II Express Briefs (4) (2006)
Xianlong Hong, Yici Cai, Hailong Yao, Duo Li
DFM-aware Routing for Yield Enhancement. APCCAS (2006)
Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hong, Xiaodong Hu, Guiying Yan
DraXRouter: global routing in X-Architecture with dynamic resource assignment. ASP-DAC (2006)
Lijuan Luo, Qiang Zhou, Yici Cai, Xianlong Hong, Yibo Wang
A novel technique integrating buffer insertion into timing driven placement. ISCAS (2006)
Sheqin Dong, Fan Guo, Jun Yuan, Rensheng Wang, Xianlong Hong
Stochastic Local Search Using the Search Space Smoothing Meta-Heuristic: A Case Study. JCIS (2006)
Hailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong
Multilevel Routing With Redundant Via Insertion. IEEE Trans. Circuits Syst. II Express Briefs (10) (2006)

Xianlong Hong.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Xianlong Hong