Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction.
Weixiang ShenYici CaiXianlong HongJiang HuPublished in: ISVLSI (2007)
Keyphrases
- low power
- tree construction
- power consumption
- high speed
- decision trees
- low cost
- suffix tree
- r tree
- high power
- single chip
- power saving
- low power consumption
- real time
- power reduction
- digital signal processing
- wireless transmission
- vlsi circuits
- signal processor
- gate array
- logic circuits
- power dissipation
- pattern recognition
- mixed signal
- signal processing
- data structure
- feature selection