Sheqin Dong

Publication Activity (10 Years)

Years Active: 2000-2024
Publications (10 Years): 8

Top Venues

CoRR

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

ISQED

ISCAS

Publications

Zhenyi Gao, Sheqin Dong, Zifei Cheng, Wenjian Yu
MORE-Router+: Multilayer Multi-capacity ORdered Escape Routing via Bus-oriented Layer Assignment. ISQED (2024)
Zhenyi Gao, Sheqin Dong, Zhicong Tang, Wenjian Yu
MC-MCF: A Multi-Capacity Model for Ordered Escape Routing. ISQED (2023)
Zhaopo Liao, Sheqin Dong
A Constraint-Driven Compact Model with Partition Strategy for Ordered Escape Routing. ACM Great Lakes Symposium on VLSI (2020)
Fengxian Jiao, Sheqin Dong
Ordered Escape Routing with Consideration of Differential Pair and Blockage. ACM Trans. Design Autom. Electr. Syst. 23 (4) (2018)
Fengxian Jiao, Sheqin Dong, Bei Yu, Bing Li, Ulf Schlichtmann
Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips. ISCAS (2018)
Qian Chen, Sheqin Dong
A Novel Mixed-Size Fixed-Outline Floorplacement Algorithm. ISVLSI (2018)
Kan Wang, Sheqin Dong, Fengxian Jiao
TSF3D: MSV-Driven Power Optimization for Application-Specific 3D Network-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (7) (2017)
Fengxian Jiao, Sheqin Dong
Ordered Escape routing for grid pin array based on Min-cost Multi-commodity Flow. ASP-DAC (2016)
Sheqin Dong, Jianchang Ao, Fuqi Luo
Delay-Driven and Antenna-Aware Layer Assignment in Global Routing Under Multitier Interconnect Structure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (5) (2015)
Kan Wang, Sheqin Dong
Post-floorplanning power optimization for MSV-driven application specific NoC design. ISCAS (2014)
Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto
Voltage and Level-Shifter Assignment Driven Floorplanning. CoRR (2014)
Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto
Floorplanning and Topology Generation for Application-Specific Network-on-Chip. CoRR (2014)
Kan Wang, Sheqin Dong, Huaxi Wang, Qian Chen, Tao Lin
Mixed-Crossing-Avoided Escape Routing of Mixed-Pattern Signals on Staggered-Pin-Array PCBs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (4) (2014)
Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto
Network flow-based simultaneous retiming and slack budgeting for low power design. CoRR (2014)
Bei Yu, Sheqin Dong, Satoshi Goto
Multi-Voltage and Level-Shifter Assignment Driven Floorplanning. CoRR (2014)
Kan Wang, Sheqin Dong
Power optimization for application-specific 3D network-on-chip with multiple supply voltages. ASP-DAC (2013)
Kan Wang, Huaxi Wang, Sheqin Dong
Escape routing of mixed-pattern signals based on staggered-pin-array PCBs. ISPD (2013)
Jianchang Ao, Sheqin Dong, Song Chen, Satoshi Goto
Delay-driven layer assignment in global routing under multi-tier interconnect structure. ISPD (2013)
Wenxu Sheng, Sheqin Dong
Multi-bend bus-driven floorplanning considering fixed-outline constraints. Integr. 46 (2) (2013)
Tao Lin, Sheqin Dong, Song Chen, Satoshi Goto
Linear optimal one-sided single-detour algorithm for untangling twisted bus. ASP-DAC (2012)
Haiqi Wang, Sheqin Dong, Tao Lin, Song Chen, Satoshi Goto
Novel Voltage Choice and Min-Cut Based Assignment for Dual-VDD System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2012)
Wei Zhong, Takeshi Yoshimura, Bei Yu, Song Chen, Sheqin Dong, Satoshi Goto
Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips. IEICE Trans. Electron. (4) (2012)
Kan Wang, Sheqin Dong, Yuchun Ma, Satoshi Goto, Jason Cong
Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs. ISQED (2012)
Kan Wang, Sheqin Dong, Satoshi Goto
Voltage island-driven power optimization for application specific network-on-chip design. ACM Great Lakes Symposium on VLSI (2012)
Ou He, Sheqin Dong, Wooyoung Jang, Jinian Bian, David Z. Pan
UNISM: Unified Scheduling and Mapping for General Networks on Chip. IEEE Trans. Very Large Scale Integr. Syst. 20 (8) (2012)
Tao Lin, Sheqin Dong, Song Chen, Yuchun Ma, Ou He, Satoshi Goto
Novel and efficient min cut based voltage assignment in gate level. ISQED (2011)
Kan Wang, Sheqin Dong, Yuchun Ma, Yu Wang, Xianlong Hong, Jason Cong
Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2011)
Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto
Network flow-based simultaneous retiming and slack budgeting for low power design. ASP-DAC (2011)
Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong
Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs. ASP-DAC (2011)
Wei Zhong, Bei Yu, Song Chen, Takeshi Yoshimura, Sheqin Dong, Satoshi Goto
Application-specific Network-on-Chip synthesis: Cluster generation and network component insertion. ISQED (2011)
Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto
Buffer Planning for IP Placement Using Sliced-LFF. VLSI Design 2011 (2011)
Jianchang Ao, Sheqin Dong, Song Chen, Satoshi Goto
Through-Silicon-Via assignment for 3D ICs. ASICON (2011)
Wenxu Sheng, Sheqin Dong, Yuliang Wu, Satoshi Goto
Fixed outline multi-bend bus driven floorplanning. ISQED (2010)
Xu He, Sheqin Dong, Yuchun Ma
Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs. Integr. 43 (4) (2010)
Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng
Bus via reduction based on floorplan revising. ACM Great Lakes Symposium on VLSI (2010)
Wentao Sui, Sheqin Dong, Jinian Bian
Wirelength-driven force-directed 3D FPGA placement. ACM Great Lakes Symposium on VLSI (2010)
Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto
Floorplanning and topology generation for application-specific network-on-chip. ASP-DAC (2010)
Tao Lin, Sheqin Dong, Bei Yu, Song Chen, Satoshi Goto
A revisit to voltage partitioning problem. ACM Great Lakes Symposium on VLSI (2010)
Xu He, Sheqin Dong, Xianlong Hong, Satoshi Goto
Integrated interlayer via planning and pin assignment for 3D ICs. SLIP (2009)
Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto
Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2009)
Bei Yu, Sheqin Dong, Satoshi Goto, Song Chen
Voltage-island driven floorplanning considering level-shifter positions. ACM Great Lakes Symposium on VLSI (2009)
Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto
Voltage and Level-Shifter Assignment Driven Floorplanning. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Sheqin Dong, Hongjie Bai, Xianlong Hong, Satoshi Goto
Buffer Planning for 3D ICs. ISCAS (2009)
Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong
Simultaneous buffer and interlayer via planning for 3D floorplanning. ISQED (2009)
Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. ASP-DAC (2008)
Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto
Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration. ISQED (2008)
Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto
Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2008)
Kang Zhao, Jinian Bian, Chenqian Jiang, Sheqin Dong, Satoshi Goto
Cache miss reduction through hardware-assisted loop optimization. CSCWD (2008)
Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto
Symmetry constraint based on mismatch analysis for analog layout in SOI technology. ASP-DAC (2008)
Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto
Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2008)
Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng
A novel fixed-outline floorplanner with zero deadspace for hierarchical design. ICCAD (2008)
Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto
HyMacs: hybrid memory access optimization based on custom-instruction scheduling. ACM Great Lakes Symposium on VLSI (2008)
Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong
An effective buffer planning algorithm for IP based fixed-outline SOC placement. ACM Great Lakes Symposium on VLSI (2007)
Lingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma
A Fast 3D-BSG Algorithm for 3D Packing Problem. ISCAS (2007)
Yaoguang Wei, Sheqin Dong, Xianlong Hong
APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement. Integr. 40 (4) (2007)
Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong
Interconnect Power Optimization Based on Timing Analysis. ISVLSI (2007)
Kang Zhao, Jinian Bian, Sheqin Dong
A Fast Custom Instructions Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design. CSCWD (2007)
Yaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma
An accurate and efficient probabilistic congestion estimation model in x architecture. SLIP (2007)
Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. ASP-DAC (2007)
Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong
Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation. ASP-DAC (2007)
Hongjie Bai, Sheqin Dong, Xianlong Hong
Congestion Driven Buffer Planning for X-Architecture. ISQED (2007)
Sheqin Dong, Fan Guo, Jun Yuan, Rensheng Wang, Xianlong Hong
Stochastic Local Search Using the Search Space Smoothing Meta-Heuristic: A Case Study. JCIS (2006)
Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen
Buffer planning based on block exchanging. ISCAS (2006)
Di Long, Xianlong Hong, Sheqin Dong
Signal-path driven partition and placement for analog circuit. ASP-DAC (2006)
Song Chen, Sheqin Dong, Xianlong Hong, Yuchun Ma, Chung-Kuan Cheng
VLSI Block Placement With Alignment Constraints. IEEE Trans. Circuits Syst. II Express Briefs (8) (2006)
Sheqin Dong, Shuyi Zheng, Xianlong Hong
Floorplanning for 2.5-D system integration using multi-layer-BSG structure. ISCAS (2006)
Sheqin Dong, Fan Guo, Jun Yuan, Rensheng Wang, Xianlong Hong
A Novel Tour Construction Heuristic for Traveling Salesman Problem Using LFF Principle. JCIS (2006)
Liu Yang, Sheqin Dong, Xianlong Hong, Yuchun Ma
A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints. APCCAS (2006)
Shaojun Wei, Sheqin Dong, Xianlong Hong, Youliang Wu
On handling the fixed-outline constraints of floorplanning using less flexibility first principles. ISCAS (2006)
Sheqin Dong, Rensheng Wang, Fan Guo, Jun Yuan, Xianlong Hong
Floorplanning by A Revised 3-D Corner Block List with sub-C+-tree. JCIS (2006)
Kang Zhao, Jinian Bian, Sheqin Dong
A Heterogeneous Dependency Graph as Intermediate Representation for Instruction Set Customization. JCIS (2006)
Yuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu
General Floorplans with L/T-Shaped Blocks Using Corner Block List. J. Comput. Sci. Technol. 21 (6) (2006)
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng
Performance constrained floorplanning based on partial clustering [IC layout]. ISCAS (2) (2005)
Renshen Wang, Sheqin Dong, Xianlong Hong
An improved P-admissible floorplan representation based on Corner Block List. ASP-DAC (2005)
Zhe Zhou, Sheqin Dong, Xianlong Hong, Yuliang Wu, Yoji Kajitani
A new approach based on LFF for optimization of dynamic hardware reconfigurations. ISCAS (2) (2005)
Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu
LFF algorithm for heterogeneous FPGA floorplanning. ASP-DAC (2005)
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng
Buffer Planning Algorithm Based on Partial Clustered Floorplanning. ISQED (2005)
Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen
A New Buffer Planning Algorithm Based on Room Resizing. EUC (2005)
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu
Buffer planning as an Integral part of floorplanning with consideration of routing congestion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (4) (2005)
Rong Liu, Sheqin Dong, Xianlong Hong
An efficient algorithm to fixed-outline floorplanning based on instance augmentation. CAD/Graphics (2005)
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng
Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. ISQED (2005)
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng
VLSI block placement with alignment constraints based on corner block list. ISCAS (6) (2005)
Rong Liu, Sheqin Dong, Xianlong Hong
Fixed-outline floorplanning based on common subsequence. ACM Great Lakes Symposium on VLSI (2005)
Rong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani
Fixed-outline floorplanning with constraints through instance augmentation. ISCAS (2) (2005)
Di Long, Xianlong Hong, Sheqin Dong
Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit. ISCAS (3) (2005)
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
A buffer planning algorithm with congestion optimization. ASP-DAC (2004)
Xianlong Hong, Sheqin Dong, Gang Huang, Yici Cai, Chung-Kuan Cheng, Jun Gu
Corner block list representation and its application to floorplan optimization. IEEE Trans. Circuits Syst. II Express Briefs (5) (2004)
Sheqin Dong, Zhong Yang, Xianlong Hong, Yuliang Wu
Module placement based on quadratic programming and rectangle packing using less flexibility first principle. ISCAS (5) (2004)
Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
Stairway compaction using corner block list and its applications with rectilinear blocks. ACM Trans. Design Autom. Electr. Syst. 9 (2) (2004)
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
Buffer allocation algorithm with consideration of routing congestion. ASP-DAC (2004)
Xianlong Hong, Yuchun Ma, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
Corner block list representation and its application with boundary constraints. Sci. China Ser. F Inf. Sci. 47 (1) (2004)
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
A buffer planning algorithm for chip-level floorplanning. Sci. China Ser. F Inf. Sci. 47 (6) (2004)
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu
Fast Evaluation of Bounded Slice-Line Grid. J. Comput. Sci. Technol. 19 (6) (2004)
Sheqin Dong, Xianlong Hong, Xin Qi, Ruijie Wang, Song Chen, Jun Gu
VLSI module placement with pre-placed modules and considering congestion using solution space smoothing. ASP-DAC (2003)
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
An integrated floorplanning with an efficient buffer planning algorithm. ISPD (2003)
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
Dynamic global buffer planning optimization based on detail block locating and congestion analysis. DAC (2003)
Sheqin Dong, Xianlong Hong, Song Chen, Xin Qi, Ruijie Wang, Jun Gu
VLSI Module Placement with Pre-Placed Modules and with Consideration of Congestion Using Solution Space Smoothing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Rui Liu, Sheqin Dong, Xianlong Hong, Di Long, Jun Gu
Algorithms for analog VLSI 2D stack generation and block merging. ISCAS (4) (2003)
Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu
Arbitrary convex and concave rectilinear block packing based on corner block list. ISCAS (5) (2003)
Sheqin Dong, Xianlong Hong, Yuliang Wu, Jun Gu
Deterministic VLSI Block Placement Algorithm Using Less Flexibility First Principle. J. Comput. Sci. Technol. 18 (6) (2003)

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Publication Activity (10 Years)

Top Topics

Top Venues

Sheqin Dong