Network flow-based simultaneous retiming and slack budgeting for low power design.
Bei YuSheqin DongYuchun MaTao LinYu WangSong ChenSatoshi GotoPublished in: CoRR (2014)
Keyphrases
- low power
- network flow
- single chip
- high speed
- low cost
- low power consumption
- power consumption
- logic circuits
- vlsi architecture
- cmos technology
- gate array
- design process
- digital signal processing
- mixed signal
- low complexity
- computational complexity
- power reduction
- vlsi circuits
- graph cuts
- power dissipation
- dynamic programming
- lower bound
- genetic algorithm
- wireless transmission
- signal processor
- real time