Yu Hu

Publication Activity (10 Years)

Years Active: 2005-2021
Publications (10 Years): 9

Top Topics

Quantum Mechanics

Unsupervised Image Segmentation

Hardware Implementation

Top Venues

ACM J. Emerg. Technol. Comput. Syst.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

IEEE Embed. Syst. Lett.

Publications

Wentao Chen, Hailong Qiu, Jian Zhuang, Chutong Zhang, Yu Hu, Qing Lu, Tianchen Wang, Yiyu Shi, Meiping Huang, Xiaowei Xu
Quantization of Deep Neural Networks for Accurate Edge Computing. ACM J. Emerg. Technol. Comput. Syst. 17 (4) (2021)
Xiaowei Xu, Feng Lin, Wenyao Xu, Xin-Wei Yao, Yiyu Shi, Dewen Zeng, Yu Hu
MDA: A Reconfigurable Memristor-Based Distance Accelerator for Time Series Mining on Data Centers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (5) (2019)
Xiaowei Xu, Qing Lu, Tianchen Wang, Yu Hu, Chen Zhuo, Jinglan Liu, Yiyu Shi
Efficient Hardware Implementation of Cellular Neural Networks with Incremental Quantization and Early Exit. ACM J. Emerg. Technol. Comput. Syst. 14 (4) (2018)
Xiaowei Xu, Qing Lu, Yu Hu, Lin Yang, Xiaobo Sharon Hu, Danny Ziyi Chen, Yiyu Shi
Quantization of Fully Convolutional Networks for Accurate Biomedical Image Segmentation. CoRR (2018)
Xiaowei Xu, Qing Lu, Lin Yang, Xiaobo Sharon Hu, Danny Z. Chen, Yu Hu, Yiyu Shi
Quantization of Fully Convolutional Networks for Accurate Biomedical Image Segmentation. CVPR (2018)
Xiaowei Xu, Feng Lin, Aosen Wang, Xin-Wei Yao, Qing Lu, Wenyao Xu, Yiyu Shi, Yu Hu
Accelerating Dynamic Time Warping With Memristor-Based Customized Fabrics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (4) (2018)
Xiaowei Xu, Qing Lu, Tianchen Wang, Jinglan Liu, Yu Hu, Yiyu Shi
Efficient hardware implementation of cellular neural networks with powers-of-two based incremental quantization. NCS (2017)
Xiaowei Xu, Dewen Zeng, Wenyao Xu, Yiyu Shi, Yu Hu
An Efficient Memristor-based Distance Accelerator for Time Series Data Mining on Data Centers. DAC (2017)
Xiaowei Xu, Feng Lin, Aosen Wang, Yu Hu, Ming-Chun Huang, Wenyao Xu
Body-Earth Mover's Distance: A Matching-Based Approach for Sleep Posture Recognition. IEEE Trans. Biomed. Circuits Syst. 10 (5) (2016)
Hanqing Zhou, Xiaowei Xu, Yu Hu, Guangyu Yu, Zeyu Yan, Feng Lin, Wenyao Xu
Energy-efficient pipelined DTW architecture on hybrid embedded platforms. IGSC (2015)
Xiaowei Xu, Feng Lin, Aosen Wang, Chen Song, Yu Hu, Wenyao Xu
On-bed sleep posture recognition based on body-earth mover's distance. BioCAS (2015)
Chaofan Yu, Lingli Wang, Chun Zhang, Yu Hu, Lei He
Fast Filter-Based Boolean Matchers. IEEE Embed. Syst. Lett. 5 (4) (2013)
Sina Basir-Kazeruni, Hao Yu, Fang Gong, Yu Hu, Chunchen Liu, Lei He
SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty. Integr. 46 (1) (2013)
Tianyun Zhang, Rui Zhang, Lingli Wang, Yu Hu
A method to build reconfigurable architectures by extracting common subgraphs. ASICON (2011)
Zhe Feng, Naifeng Jing, GengSheng Chen, Yu Hu, Lei He
IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs. FPL (2011)
Lei He, Shauki Elassaad, Yiyu Shi, Yu Hu, Wei Yao
System-in-Package: Electrical and Layout Perspectives. Found. Trends Electron. Des. Autom. 4 (4) (2011)
Wenyao Xu, Jia Wang, Yu Hu, Ju-Yueh Lee, Fang Gong, Lei He, Majid Sarrafzadeh
In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2011)
Lintao Cui, Jing Chen, Yu Hu, Jinjun Xiong, Zhe Feng, Lei He
Acceleration of Multi-agent Simulation on FPGAs. FPL (2011)
Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He, Minming Li
Fault-tolerant resynthesis with dual-output LUTs. ASP-DAC (2010)
Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong
Accelerating Boolean Matching Using Bloom Filter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (10) (2010)
Samuel B. Luckenbill, Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He
RALF: Reliability Analysis for Logic Faults - An exact algorithm and its applications. DATE (2010)
Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong
Engineering a scalable Boolean matching based on EDA SaaS 2.0. ICCAD (2010)
Manu Jose, Yu Hu, Rupak Majumdar, Lei He
Rewiring for robustness. DAC (2010)
Manu Jose, Yu Hu, Rupak Majumdar
On power and fault-tolerance optimization in FPGA physical synthesis. ICCAD (2010)
Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong
Building a faster boolean matcher using bloom filter. FPGA (2010)
Yu Hu, Satyaki Das, Steven Trimberger, Lei He
Design and Synthesis of Programmable Logic Block With Mixed LUT and Macrogate. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (4) (2009)
Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He
Simultaneous test pattern compaction, ordering and X-filling for testing power reduction. ISQED (2009)
Zhe Feng, Yu Hu, Lei He, Rupak Majumdar
IPR: In-Place Reconfiguration for FPGA fault tolerance. ICCAD (2009)
Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti, Yu Hu
Worst case timing jitter and amplitude noise in differential signaling. ISQED (2009)
King Ho Tam, Yu Hu, Lei He, Tom Tong Jing, Xinyi Zhang
Buffer Insertion for Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (8) (2008)
Yu Hu, Zhe Feng, Lei He, Rupak Majumdar
Robust FPGA resynthesis based on fault-tolerant Boolean matching. ICCAD (2008)
Yu Hu, Yan Lin, Lei He, Tim Tuan
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming. ACM Trans. Design Autom. Electr. Syst. 13 (2) (2008)
Tom Tong Jing, Yu Hu, Zhe Feng, Xianlong Hong, Xiaodong Hu, Guiying Yan
A full-scale solution to the rectilinear obstacle-avoiding Steiner problem. Integr. 41 (3) (2008)
Yu Hu, Victor Shih, Rupak Majumdar, Lei He
FPGA area reduction by multi-output function based sequential resynthesis. DAC (2008)
Yu Hu, Victor Shih, Rupak Majumdar, Lei He
Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (10) (2008)
Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Zhe Feng, Lei He, Xianlong Hong
Fashion: A Fast and Accurate Solution to Global Routing Problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (4) (2008)
Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, Xianlong Hong
DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. ASP-DAC (2007)
Tom Tong Jing, Zhe Feng, Yu Hu, Xianlong Hong, Xiaodong Hu, Guiying Yan
lambda-OAT: lambda-Geometry Obstacle-Avoiding Tree Construction With O(nlog n) Complexity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (11) (2007)
Hao Yu, Yu Hu, Chunchen Liu, Lei He
Minimal skew clock embedding considering time variant temperature gradient. ISPD (2007)
Yu Hu, Satyaki Das, Steven Trimberger, Lei He
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates. ICCAD (2007)
Yu Hu, King Ho Tam, Tong Jing, Lei He
Fast dual-vdd buffering based on interconnect prediction and sampling. SLIP (2007)
Yu Hu, Victor Shih, Rupak Majumdar, Lei He
Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping. ICCAD (2007)
Yu Hu, Tong Jing, Zhe Feng, Xianlong Hong, Xiaodong Hu, Guiying Yan
ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm. J. Comput. Sci. Technol. 21 (1) (2006)
Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hong, Xiaodong Hu, Guiying Yan
DraXRouter: global routing in X-Architecture with dynamic resource assignment. ASP-DAC (2006)
Yu Hu, Yan Lin, Lei He, Tim Tuan
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction. DAC (2006)
Zhe Feng, Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan
) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane. ISPD (2006)
Yan Lin, Yu Hu, Lei He, Vijay Raghunat
An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction. ISLPED (2006)
Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu, Xiaodong Hu, Guiying Yan
Via-Aware Global Routing for Good VLSI Manufacturability and High Yield. ASAP (2005)
Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan
A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design. SAMOS (2005)
Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, Guiying Yan
An-OARSMan: obstacle-avoiding routing tree construction with good length performance. ASP-DAC (2005)