Yan Lin

Publication Activity (10 Years)

Years Active: 2004-2012
Publications (10 Years): 0

Top Topics

Statistical Information

Optimization Methods

Hardware Design

Fpga Implementation

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

Publications

Lerong Cheng, Wenyao Xu, Fang Gong, Yan Lin, Ho-Yan Wong, Lei He
Statistical Timing and Power Optimization of Architecture and Device for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 5 (2) (2012)
Yan Lin, Lei He, Mike Hutton
Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 16 (2) (2008)
Lerong Cheng, Yan Lin, Lei He
Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. FPGA (2008)
Yu Hu, Yan Lin, Lei He, Tim Tuan
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming. ACM Trans. Design Autom. Electr. Syst. 13 (2) (2008)
Fei Li, Yan Lin, Lei He
Field Programmability of Supply Voltages for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (4) (2007)
Yan Lin, Lei He
Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation. FPGA (2007)
Lerong Cheng, Fei Li, Yan Lin, Phoebe Wong, Lei He
Device and Architecture Cooptimization for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (7) (2007)
Yan Lin, Mike Hutton, Lei He
Statistical placement for FPGAs considering. IET Comput. Digit. Tech. 1 (4) (2007)
Yan Lin, Lei He
Device and architecture concurrent optimization for FPGA transient soft error rate. ICCAD (2007)
Yan Lin, Lei He
Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction. DATE (2007)
Yan Lin, Lei He
Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (10) (2006)
Yu Hu, Yan Lin, Lei He, Tim Tuan
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction. DAC (2006)
Yan Lin, Yu Hu, Lei He, Vijay Raghunat
An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction. ISLPED (2006)
Mike Hutton, Yan Lin, Lei He
Placement and Timing for FPGAs Considering Variations. FPL (2006)
Yan Lin, Fei Li, Lei He
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction. ASP-DAC (2005)
Yan Lin, Fei Li, Lei He
Circuits and architectures for field programmable gate array with configurable supply voltage. IEEE Trans. Very Large Scale Integr. Syst. 13 (9) (2005)
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
Device and architecture co-optimization for FPGA power reduction. DAC (2005)
Yan Lin, Lei He
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction. DAC (2005)
Yan Lin, Fei Li, Lei He
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability. FPGA (2005)
Ho-Yan Wong, Lerong Cheng, Yan Lin, Lei He
FPGA device and architecture evaluation considering process variations. ICCAD (2005)
Fei Li, Yan Lin, Lei He, Jason Cong
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. FPGA (2004)
Fei Li, Yan Lin, Lei He
FPGA power reduction using configurable dual-Vdd. DAC (2004)
Fei Li, Yan Lin, Lei He
Vdd programmability to reduce FPGA interconnect power. ICCAD (2004)