Device and Architecture Cooptimization for FPGA Power Reduction.
Lerong ChengFei LiYan LinPhoebe WongLei HePublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2007)
Keyphrases
- power reduction
- power consumption
- low power
- multithreading
- power saving
- hardware implementation
- hardware architecture
- high speed
- real time
- hardware design
- energy efficiency
- multi threaded
- fine grained
- data center
- scheduling algorithm
- data flow
- field programmable gate array
- power dissipation
- low cost
- object oriented
- mobile devices