Fei Li

Publication Activity (10 Years)

Years Active: 2001-2011
Publications (10 Years): 0

Publications

Jonathan W. Greene, Sinan Kaptanoglu, Wenyi Feng, Volker Hecht, Joel Landry, Fei Li, Anton Krouglyanskiy, Mihai Morosan, Val Pevzner
A 65nm flash-based FPGA fabric optimized for low cost and power. FPGA (2011)
Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li, Chi-Chen Peng
Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (11) (2010)
Fei Li, Yan Lin, Lei He
Field Programmability of Supply Voltages for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (4) (2007)
Lerong Cheng, Fei Li, Yan Lin, Phoebe Wong, Lei He
Device and Architecture Cooptimization for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (7) (2007)
Jennifer L. Wong, Weiping Liao, Fei Li, Lei He, Miodrag Potkonjak
Scheduling of Soft Real-Time Systems for Context-Aware Applications. DATE (2005)
Yan Lin, Fei Li, Lei He
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction. ASP-DAC (2005)
Yan Lin, Fei Li, Lei He
Circuits and architectures for field programmable gate array with configurable supply voltage. IEEE Trans. Very Large Scale Integr. Syst. 13 (9) (2005)
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
Device and architecture co-optimization for FPGA power reduction. DAC (2005)
Yan Lin, Fei Li, Lei He
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability. FPGA (2005)
Fei Li, Yizhou Lin, Lei He, Deming Chen, Jason Cong
Power modeling and characteristics of field programmable gate arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (11) (2005)
Fei Li, Yan Lin, Lei He, Jason Cong
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. FPGA (2004)
Deming Chen, Jason Cong, Fei Li, Lei He
Low-power technology mapping for FPGA architectures with dual supply voltages. FPGA (2004)
Fei Li, Yan Lin, Lei He
FPGA power reduction using configurable dual-Vdd. DAC (2004)
Fei Li, Yan Lin, Lei He
Vdd programmability to reduce FPGA interconnect power. ICCAD (2004)
Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel, Hema Ramamurthy
High-level area and power-up current estimation considering rich cell library. ASP-DAC (2004)
Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel, Hema Ramamurthy
High Level Area and Current Estimation. PATMOS (2003)
Weiping Liao, Fei Li, Lei He
Microarchitecture level power and thermal simulation considering temperature dependent leakage model. ISLPED (2003)
Fei Li, Deming Chen, Lei He, Jason Cong
Architecture evaluation for power-efficient FPGAs. FPGA (2003)
Fei Li, Lei He, Kewal K. Saluja
Estimation of Maximum Power-Up Current. VLSI Design (2002)
Fei Li, Lei He
Maximum current estimation considering power gating. ISPD (2001)