Login / Signup
Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction.
Yan Lin
Lei He
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2006)
Keyphrases
</>
power reduction
power dissipation
high speed
power consumption
low power
power saving
single chip
cmos technology
low cost
signal processing
finite state machines
multithreading
low power consumption
peak load
fine grained