Low power clock buffer planning methodology in F-D placement for large scale circuit design.
Yanfeng WangQiang ZhouYici CaiJiang HuXianlong HongJinian BianPublished in: ASP-DAC (2008)
Keyphrases
- low power
- circuit design
- power consumption
- high speed
- low cost
- digital signal processing
- single chip
- mixed signal
- vlsi circuits
- digital circuits
- high power
- wireless transmission
- design automation
- energy efficiency
- low power consumption
- power reduction
- power saving
- real time
- vlsi architecture
- ultra low power
- cmos technology
- design methodology
- general purpose
- logic circuits
- multi channel
- embedded systems
- gate array