Wai-Kei Mak

Publication Activity (10 Years)

Years Active: 1990-2024
Publications (10 Years): 29

Top Topics

Reinforcement Learning

Highly Efficient

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Tzu-Chuan Lin, Fang-Yu Hsu, Wai-Kei Mak, Ting-Chi Wang
An Effective Netlist Planning Approach for Double-sided Signal Routing. ASPDAC (2024)
Fang-Yu Hsu, Tzu-Chuan Lin, Wai-Kei Mak, Ting-Chi Wang
A Bounding Box-based Net Partitioning Method for Double-sided Routing. ACM Great Lakes Symposium on VLSI (2024)
Ching-Yao Huang, Wai-Kei Mak
CTQr: Control and Timing-Aware Qubit Routing. ASPDAC (2024)
Ching-Yao Huang, Wai-Kei Mak
Row Planning and Placement for Hybrid-Row-Height Designs. ASPDAC (2024)
Bing-Huan Wu, Wai-Kei Mak
Optimization for Buffer and Splitter Insertion in AQFP Circuits with Local and Group Movement. ISPD (2024)
Syuan-Han Liang, Tsu-Ling Hsiung, Wai-Kei Mak, Ting-Chi Wang
Hybrid-Row-Height Design Placement Legalization Considering Cell Variants. ACM Great Lakes Symposium on VLSI (2023)
Yu-Jin Xie, Wai-Kei Mak
Drain-to-Drain Abutment-Aware Detailed Placement Refinement for Power Staple Insertion Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (4) (2023)
Meng-Yun Liu, Yu-Cheng Lai, Wai-Kei Mak, Ting-Chi Wang
Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization. ICCAD (2022)
Chung-Hsien Wu, Wai-Kei Mak, Chris Chu
Linear-time Mixed-Cell-Height Legalization for Minimizing Maximum Displacement. ISPD (2022)
Kuan-Yu Chen, Hsiu-Chu Hsu, Wai-Kei Mak, Ting-Chi Wang
HybridGP: Global Placement for Hybrid-Row-Height Designs. ASP-DAC (2022)
Ching-Yao Huang, Chi-Hsiang Lien, Wai-Kei Mak
Reinforcement Learning and DEAR Framework for Solving the Qubit Mapping Problem. ICCAD (2022)
Ching-Cheng Wang, Wai-Kei Mak
A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum (SFQ) Logic Circuits. ICCAD (2021)
Bo-Yang Chen, Chi-Chun Fang, Wai-Kei Mak, Ting-Chi Wang
Multiple-Layer Multiple-Patterning Aware Placement Refinement for Mixed-Cell-Height Designs. ISPD (2021)
Yu-Jin Xie, Kuan-Yu Chen, Wai-Kei Mak
Manufacturing-Aware Power Staple Insertion Optimization by Enhanced Multi-Row Detailed Placement Refinement. ASP-DAC (2021)
Yu-Chen Liao, Wai-Kei Mak
Pin Assignment Optimization for Multi-2.5D FPGA-Based Systems With Time-Multiplexed I/Os. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (3) (2021)
Wan-Sin Kuo, Shi-Han Zhang, Wai-Kei Mak, Richard Sun, Yoon Kah Leow
Pin Assignment Optimization for Multi-2.5D FPGA-based Systems. ISPD (2018)
Yu-Hsiang Cheng, Ding-Wei Huang, Wai-Kei Mak, Ting-Chi Wang
A practical detailed placement algorithm under multi-cell spacing constraints. ICCAD (2018)
Yixiao Ding, Chris Chu, Wai-Kei Mak
Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability Consideration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (3) (2018)
Po-Yi Wu, Wai-Kei Mak, Ting-Chi Wang, Cheng Zhuo, Kassan Unda, Yiyu Shi
A routing framework for technology migration with bump encroachment. Integr. 58 (2017)
Wai-Kei Mak, Wan-Sin Kuo, Shi-Han Zhang, Seong-I Lei, Chris Chu
Minimum Implant Area-Aware Placement and Threshold Voltage Refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (7) (2017)
Lang Feng, Yujie Wang, Jiang Hu, Wai-Kei Mak, Jeyavijayan Rajendran
Making split fabrication synergistically secure and manufacturable. ICCAD (2017)
Yixiao Ding, Chris Chu, Wai-Kei Mak
Pin Accessibility-Driven Detailed Placement Refinement. ISPD (2017)
Lang Feng, Yujie Wang, Jiang Hu, Wai-Kei Mak, Jeyavijayan Rajendran
Making split fabrication synergistically secure and manufacturable. ICCAD (2017)
Chung-Yao Hung, Peng-Yi Chou, Wai-Kei Mak
Optimizing DSA-MP decomposition and redundant via insertion with dummy vias. ASP-DAC (2017)
Chung-Yao Hung, Peng-Yi Chou, Wai-Kei Mak
Mixed-Cell-Height Standard Cell Placement Legalization. ACM Great Lakes Symposium on VLSI (2017)
Yixiao Ding, Chris Chu, Wai-Kei Mak
Self-Aligned Double Patterning Lithography Aware Detailed Routing With Color Preassignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (8) (2017)
Yixiao Ding, Chris C. N. Chu, Wai-Kei Mak
Self-aligned double patterning-aware detailed routing with double via insertion and via manufacturability consideration. DAC (2016)
Seong-I Lei, Wai-Kei Mak, Chris Chu
Minimum implant area-aware placement and threshold voltage refinement. ASP-DAC (2016)
Seong-I Lei, Wai-Kei Mak
Optimizing Pin Assignment and Escape Routing for Blind-via-Based PCBs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (2) (2016)
Jyun-Hao Chang, Hsin-I Wu, Hsien-Lun Pai, Ren-Song Tsay, Wai-Kei Mak
Highly Efficient and Effective Approach for Synchronization-Function-Level Parallel Multicore Instruction-Set Simulations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (11) (2015)
Chris C. N. Chu, Wai-Kei Mak
Flexible Packed Stencil Design With Multiple Shaping Apertures and Overlapping Shots for E-beam Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (10) (2015)
Yixiao Ding, Chris C. N. Chu, Wai-Kei Mak
Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography. DAC (2015)
Chung-Hao Tsai, Wai-Kei Mak
A fast parallel approach for common path pessimism removal. ASP-DAC (2015)
Yixiao Ding, Chris Chu, Wai-Kei Mak
Throughput Optimization for SADP and E-beam based Manufacturing of 1D Layout. DAC (2014)
Wai-Kei Mak, Chris Chu
E-Beam Lithography Character and Stencil Co-Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (5) (2014)
Seong-I Lei, Chris Chu, Wai-Kei Mak
Double patterning-aware detailed routing with mask usage balancing. ISQED (2014)
Sheng-Kai Wu, Po-Yi Hsu, Wai-Kei Mak
A novel wirelength-driven packing algorithm for FPGAs with adaptive logic modules. ASP-DAC (2014)
Chris Chu, Wai-Kei Mak
Flexible packed stencil design with multiple shaping apertures for e-beam lithography. ASP-DAC (2014)
Seong-I Lei, Wai-Kei Mak
Simultaneous Constrained Pin Assignment and Escape Routing Considering Differential Pairs for FPGA-PCB Co-Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (12) (2013)
Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak, Sheng-Hsiung Chen
MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer Rules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (10) (2013)
Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak, Sheng-Hsiung Chen
A separation and minimum wire length constrained maze routing algorithm under nanometer wiring rules. ASP-DAC (2013)
Cha-Ru Li, Wai-Kei Mak, Ting-Chi Wang
Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement. IEEE Trans. Very Large Scale Integr. Syst. 21 (3) (2013)
Wai-Kei Mak, Chris Chu
Rethinking the Wirelength Benefit of 3-D Integration. IEEE Trans. Very Large Scale Integr. Syst. 20 (12) (2012)
Yu-Yi Liang, Tien-Yu Kuo, Shao-Huan Wang, Wai-Kei Mak
ALMmap: Technology Mapping for FPGAs With Adaptive Logic Modules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (7) (2012)
Wai-Kei Mak, Yu-Chen Lin, Chris Chu, Ting-Chi Wang
Pad Assignment for Die-Stacking System-in-Package Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (11) (2012)
Shao-Huan Wang, Yu-Yi Liang, Tien-Yu Kuo, Wai-Kei Mak
ISPD11: Power-Driven Flip-Flop Merging and Relocation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (2) (2012)
Gaurav Ajwani, Chris Chu, Wai-Kei Mak
FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (2) (2011)
Jackey Z. Yan, Chris C. N. Chu, Wai-Kei Mak
SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (7) (2011)
Shao-Huan Wang, Yu-Yi Liang, Tien-Yu Kuo, Wai-Kei Mak
Power-driven flip-flop merging and relocation. ISPD (2011)
Fong-Yuan Chang, Sheng-Hsiung Chen, Ren-Song Tsay, Wai-Kei Mak
Cut-demand based routing resource allocation and consolidation for routability enhancement. ASP-DAC (2011)
Seong-I Lei, Wai-Kei Mak
Simultaneous Constrained Pin Assignment and Escape Routing for FPGA-PCB Codesign. FPL (2011)
Gaurav Ajwani, Chris Chu, Wai-Kei Mak
FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction. ISPD (2010)
De-Yu Liu, Wai-Kei Mak, Ting-Chi Wang
Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design. ACM Great Lakes Symposium on VLSI (2010)
Jackey Z. Yan, Chris Chu, Wai-Kei Mak
SafeChoice: a novel clustering algorithm for wirelength-driven placement. ISPD (2010)
Yu-Chen Lin, Wai-Kei Mak, Chris Chu, Ting-Chi Wang
Pad assignment for die-stacking System-in-Package design. ICCAD (2009)
Cheng-Yu Wang, Wai-Kei Mak
Signal skew aware floorplanning and bumper signal assignment technique for flip-chip. ASP-DAC (2009)
Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak
How to consider shorts and guarantee yield rate improvement for redundant wire insertion. ICCAD (2009)
Chun-Yu Chuang, Wai-Kei Mak
Accurate closed-form parameterized block-based statistical timing analysis applying skew-normal distribution. ISQED (2009)
George A. Constantinides, Wai-Kei Mak, Theerayod Wiangtong
Guest Editorial: Field Programmable Technology. J. Signal Process. Syst. 51 (1) (2008)
Wei-Chung Chao, Wai-Kei Mak
Low-power gated and buffered clock network construction. ACM Trans. Design Autom. Electr. Syst. 13 (1) (2008)
Wai-Kei Mak, Jr-Wei Chen
Voltage Island Generation under Performance Requirement for SoC Designs. ASP-DAC (2007)
Yi-Ru He, Wai-Kei Mak
Optimal Buffering of FPGA Interconnect for Expected Delay Optimization. FPT (2007)
Chien-Chang Chen, Wai-Kei Mak
A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers. ASP-DAC (2006)
Wai-Kei Mak
Modern FPGA constrained placement. ASP-DAC (2005)
Hao Li, Wai-Kei Mak, Srinivas Katkoori
Force-Directed Performance-Driven Placement Algorithm for FPGAs. ISVLSI (2004)
Wai-Kei Mak
I/O placement for FPGAs with multiple I/O standards. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (2) (2004)
Hao Li, Srinivas Katkoori, Wai-Kei Mak
Power minimization algorithms for LUT-based FPGA technology mapping. ACM Trans. Design Autom. Electr. Syst. 9 (1) (2004)
Wai-Kei Mak
I/O placement for FPGAs with multiple I/O standards. FPGA (2003)
Wai-Kei Mak, Evangeline F. Y. Young
Temporal logic replication for dynamically reconfigurable FPGA partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (7) (2003)
Eric S. H. Wong, Evangeline F. Y. Young, Wai-Kei Mak
Clustering based acyclic multi-way partitioning. ACM Great Lakes Symposium on VLSI (2003)
Hao Li, Wai-Kei Mak, Srinivas Katkoori
Efficient LUT-based FPGA technology mapping for power minimization. ASP-DAC (2003)
Wai-Kei Mak
Min-cut partitioning with functional replication fortechnology-mapped circuits using minimum area overhead. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (4) (2002)
Wai-Kei Mak, Evangeline F. Y. Young
Temporal logic replication for dynamically reconfigurable FPGA partitioning. ISPD (2002)
Hung-Ming Chen, D. F. Wong, Wai-Kei Mak, Hannah Honghua Yang
Faster and more accurate wiring evaluation in interconnect-centric floorplanning. ACM Great Lakes Symposium on VLSI (2001)
Wai-Kei Mak
Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead. ISPD (2001)
Wai-Kei Mak, D. F. Wong
A fast hypergraph min-cut algorithm for circuit partitioning. Integr. 30 (1) (2000)
Wai-Kei Mak, David P. Morton, R. Kevin Wood
Monte Carlo bounding techniques for determining solution quality in stochastic programs. Oper. Res. Lett. 24 (1-2) (1999)
Wai-Kei Mak, D. F. Wong
A fast hypergraph minimum cut algorithm. ISCAS (6) (1999)
Wai-Kei Mak, D. F. Wong
Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract). FPGA (1998)
Wai-Kei Mak, D. F. Wong
Performance-driven board-level routing for FPGA-based logic emulation. ICCD (1998)
Wai-Kei Mak, D. F. Wong
Board-level multiterminal net routing for FPGA-based logic emulation. ACM Trans. Design Autom. Electr. Syst. 2 (2) (1997)
Wai-Kei Mak, Martin D. F. Wong
On optimal board-level routing for FPGA-based logic emulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (3) (1997)
Wai-Kei Mak, Martin D. F. Wong
Minimum replication min-cut partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (10) (1997)
Wai-Kei Mak, D. F. Wong
Channel Segmentation Design for Symmentrical FPGAs. ICCD (1997)
Wai-Kei Mak, D. F. Wong
Minimum replication min-cut partitioning. ICCAD (1996)
Wai-Kei Mak, D. F. Wong
Board-level multi-terminal net routing for FPGA-based logic emulation. ICCAD (1995)
Wai-Kei Mak, D. F. Wong
On Optimal Board-Level Routing for FPGA-Based Logic Emulation. DAC (1995)
Mee Yee Chan, Francis Y. L. Chin, Chris Chu, Wai-Kei Mak
Dilation-5 Embedding of 3-Dimensional Grids into Hypercubes. SPDP (1993)
Richard G. Guy, John S. Heidemann, Wai-Kei Mak, Thomas W. Page Jr., Gerald J. Popek, Dieter Rothmeier
Implementation of the Ficus Replicated File System. USENIX Summer (1990)