Jeyavijayan Rajendran

ORCID

Publication Activity (10 Years)

Years Active: 2010-2024
Publications (10 Years): 71

Top Venues

CoRR

ICCAD

USENIX Security Symposium

IACR Cryptol. ePrint Arch.

Publications

Mohamadreza Rostami, Chen Chen, Rahul Kande, Huimin Li, Jeyavijayan Rajendran, Ahmad-Reza Sadeghi
Fuzzerfly Effect: Hardware Fuzzing for Memory Safety. IEEE Secur. Priv. 22 (4) (2024)
Vasudev Gohil, Satwik Patnaik, Hao Guo, Dileep Kalathil, Jeyavijayan Rajendran
DETERRENT: Detecting Trojans Using Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (1) (2024)
Vasudev Gohil, Satwik Patnaik, Dileep Kalathil, Jeyavijayan Rajendran
AttackGNN: Red-Teaming GNNs in Hardware Security Using Reinforcement Learning. USENIX Security Symposium (2024)
Matthew DeLorenzo, Vasudev Gohil, Jeyavijayan Rajendran
CreativEval: Evaluating Creativity of LLM-Based Hardware Code Generation. CoRR (2024)
Rahul Kande, Vasudev Gohil, Matthew DeLorenzo, Chen Chen, Jeyavijayan Rajendran
LLMs for Hardware Security: Boon or Bane? VTS (2024)
Mohamadreza Rostami, Marco Chilese, Shaza Zeitouni, Rahul Kande, Jeyavijayan Rajendran, Ahmad-Reza Sadeghi
Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing. CoRR (2024)
Rahul Kande, Hammond Pearce, Benjamin Tan, Brendan Dolan-Gavitt, Shailja Thakur, Ramesh Karri, Jeyavijayan Rajendran
(Security) Assertions by Large Language Models. IEEE Trans. Inf. Forensics Secur. 19 (2024)
Pallavi Borkar, Chen Chen, Mohamadreza Rostami, Nikhilesh Singh, Rahul Kande, Ahmad-Reza Sadeghi, Chester Rebeiro, Jeyavijayan Rajendran
WhisperFuzz: White-Box Fuzzing for Detecting and Locating Timing Vulnerabilities in Processors. USENIX Security Symposium (2024)
Pallavi Borkar, Chen Chen, Mohamadreza Rostami, Nikhilesh Singh, Rahul Kande, Ahmad-Reza Sadeghi, Chester Rebeiro, Jeyavijayan Rajendran
WhisperFuzz: White-Box Fuzzing for Detecting and Locating Timing Vulnerabilities in Processors. CoRR (2024)
Vasudev Gohil, Satwik Patnaik, Dileep Kalathil, Jeyavijayan Rajendran
AttackGNN: Red-Teaming GNNs in Hardware Security Using Reinforcement Learning. CoRR (2024)
Matthew DeLorenzo, Animesh Basak Chowdhury, Vasudev Gohil, Shailja Thakur, Ramesh Karri, Siddharth Garg, Jeyavijayan Rajendran
Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS. CoRR (2024)
Mohamadreza Rostami, Marco Chilese, Shaza Zeitouni, Rahul Kande, Jeyavijayan Rajendran, Ahmad-Reza Sadeghi
Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing. DATE (2024)
Vasudev Gohil, Rahul Kande, Chen Chen, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran
MABFuzz: Multi-Armed Bandit Algorithms for Fuzzing Processors. DATE (2024)
Vasudev Gohil, Rahul Kande, Chen Chen, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran
MABFuzz: Multi-Armed Bandit Algorithms for Fuzzing Processors. CoRR (2023)
Rahul Kande, Hammond Pearce, Benjamin Tan, Brendan Dolan-Gavitt, Shailja Thakur, Ramesh Karri, Jeyavijayan Rajendran
LLM-assisted Generation of Hardware Assertions. CoRR (2023)
Chen Chen, Rahul Kande, Nathan Nyugen, Flemming Andersen, Aakash Tyagi, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran
HyPFuzz: Formal-Assisted Processor Fuzzing. CoRR (2023)
Chen Chen, Vasudev Gohil, Rahul Kande, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran
PSOFuzz: Fuzzing Processors with Particle Swarm Optimization. ICCAD (2023)
Zhaokun Han, Mohammed Shayan, Aneesh Dixit, Mustafa M. Shihab, Yiorgos Makris, Jeyavijayan Rajendran
FuncTeller: How Well Does eFPGA Hide Functionality? CoRR (2023)
Zhaokun Han, Mohammed Shayan, Aneesh Dixit, Mustafa M. Shihab, Yiorgos Makris, Jeyavijayan Rajendran
FuncTeller: How Well Does eFPGA Hide Functionality? USENIX Security Symposium (2023)
Nithyashankari Gummidipoondi Jayasankaran, Hao Guo, Satwik Patnaik, Jeyavijayan Rajendran, Jiang Hu
Securing Cloud FPGAs Against Power Side-Channel Attacks: A Case Study on Iterative AES. CoRR (2023)
Chen Chen, Vasudev Gohil, Rahul Kande, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran
PSOFuzz: Fuzzing Processors with Particle Swarm Optimization. CoRR (2023)
Chen Chen, Rahul Kande, Nathan Nguyen, Flemming Andersen, Aakash Tyagi, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran
HyPFuzz: Formal-Assisted Processor Fuzzing. USENIX Security Symposium (2023)
Vasudev Gohil, Satwik Patnaik, Hao Guo, Dileep Kalathil, Jeyavijayan Rajendran
DETERRENT: Detecting Trojans using Reinforcement Learning. CoRR (2022)
Satwik Patnaik, Vasudev Gohil, Hao Guo, Jeyavijayan Rajendran
Reinforcement Learning for Hardware Security: Opportunities, Developments, and Challenges. CoRR (2022)
Vasudev Gohil, Hao Guo, Satwik Patnaik, Jeyavijayan Rajendran
ATTRITION: Attacking Static Hardware Trojan Detection Techniques Using Reinforcement Learning. CoRR (2022)
Vasudev Gohil, Hao Guo, Satwik Patnaik, Jeyavijayan Rajendran
ATTRITION: Attacking Static Hardware Trojan Detection Techniques Using Reinforcement Learning. CCS (2022)
Srini Devadas, Jeyavijayan Rajendran
Guest Editors' Introduction: Special Issue on 2021 Top Picks in Hardware and Embedded Security. IEEE Des. Test 39 (4) (2022)
Swarup Bhunia, Amitabh Das, Saverio Fazzari, Vivian Kammler, David Kehlet, Jeyavijayan Rajendran, Ankur Srivastava
Hardware IP Protection against Confidentiality Attacks and Evolving Role of CAD Tool. ICCAD (2022)
Aakash Tyagi, Addison Crump, Ahmad-Reza Sadeghi, Garrett Persyn, Jeyavijayan Rajendran, Patrick Jauernig, Rahul Kande
TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities. CoRR (2022)
Rahul Kande, Addison Crump, Garrett Persyn, Patrick Jauernig, Ahmad-Reza Sadeghi, Aakash Tyagi, Jeyavijayan Rajendran
TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities. USENIX Security Symposium (2022)
Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran
Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction. IEEE Trans. Emerg. Top. Comput. 10 (1) (2022)
Vasudev Gohil, Mark Tressler, Kevin Sipple, Satwik Patnaik, Jeyavijayan Rajendran
Games, Dollars, Splits: A Game-Theoretic Analysis of Split Manufacturing. IEEE Trans. Inf. Forensics Secur. 16 (2021)
Ahmad-Reza Sadeghi, Jeyavijayan Rajendran, Rahul Kande
Organizing The World's Largest Hardware Security Competition: Challenges, Opportunities, and Lessons Learned. ACM Great Lakes Symposium on VLSI (2021)
Adriana C. Sanabria-Borbon, Nithyashankari Gummidipoondi Jayasankaran, Jiang Hu, Jeyavijayan Rajendran, Edgar Sánchez-Sinencio
Analog/RF IP Protection: Attack Models, Defense Techniques, and Challenges. IEEE Trans. Circuits Syst. II Express Briefs 68 (1) (2021)
Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran
Removal Attacks on Logic Locking and Camouflaging Techniques. IEEE Trans. Emerg. Top. Comput. 8 (2) (2020)
Chenglu Jin, Vasudev Gohil, Ramesh Karri, Jeyavijayan Rajendran
Security of Cloud FPGAs: A Survey. CoRR (2020)
Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Amr Abuellil, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran
Breaking Analog Locking Techniques. IEEE Trans. Very Large Scale Integr. Syst. 28 (10) (2020)
Benjamin Tan, Ramesh Karri, Nimisha Limaye, Abhrajit Sengupta, Ozgur Sinanoglu, Md Moshiur Rahman, Swarup Bhunia, Danielle Duvalsaint, Ronald D. Blanton, Amin Rezaei, Yuanqi Shen, Hai Zhou, Leon Li, Alex Orailoglu, Zhaokun Han, Austin Benedetti, Luciano Brignone, Muhammad Yasin, Jeyavijayan Rajendran, Michael Zuzak, Ankur Srivastava, Ujjwal Guin, Chandan Karfa, Kanad Basu, Vivek V. Menon, Matthew French, Peilin Song, Franco Stellari, Gi-Joon Nam, Peter Gadfort, Alric Althoff, Joseph Tostenrude, Saverio Fazzari, Eric Breckenfeld, Kenneth Plaks
Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking. CoRR (2020)
Chaofei Yang, Beiye Liu, Hai Li, Yiran Chen, Mark Barnell, Qing Wu, Wujie Wen, Jeyavijayan Rajendran
Thwarting Replication Attack Against Memristor-Based Neuromorphic Computing System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Abhishek Chakraborty, Nithyashankari Gummidipoondi Jayasankaran, Yuntao Liu, Jeyavijayan Rajendran, Ozgur Sinanoglu, Ankur Srivastava, Yang Xie, Muhammad Yasin, Michael Zuzak
Keynote: A Disquisition on Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Amr Abuellil, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran
Breaking Analog Locking Techniques via Satisfiability Modulo Theories. ITC (2019)
Ghada Dessouky, David Gens, Patrick Haney, Garrett Persyn, Arun K. Kanuparthi, Hareesh Khattri, Jason M. Fung, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran
HardFails: Insights into Software-Exploitable Hardware Bugs. USENIX Security Symposium (2019)
Wenbin Xu, Lang Feng, Jeyavijayan Rajendran, Jiang Hu
Layout recognition attacks on split manufacturing. ASP-DAC (2019)
Ryan Vrecenar, Michael Hall, Joshua Zshiesche, Mahesh Naidu, Jeyavijayan Rajendran, Stavros Kalafatis
Red Teaming a Multi-Colored Bluetooth Bulb. ICCD (2019)
Ghada Dessouky, David Gens, Patrick Haney, Garrett Persyn, Arun K. Kanuparthi, Hareesh Khattri, Jason M. Fung, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran
When a Patch is Not Enough - HardFails: Software-Exploitable Hardware Bugs. CoRR (2018)
Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran
Towards provably-secure analog and mixed-signal locking against overproduction. ICCAD (2018)
Ro Cammarota, Naghmeh Karimi, Siddharth Garg, Jeyavijayan Rajendran
Special session: Recent developments in hardware security. VTS (2018)
Yujie Wang, Pu Chen, Jiang Hu, Guofeng Li, Jeyavijayan Rajendran
The Cat and Mouse in Split Manufacturing. IEEE Trans. Very Large Scale Integr. Syst. 26 (5) (2018)
Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran
Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction. IACR Cryptol. ePrint Arch. 2018 (2018)
Murugappan Alagappan, Jeyavijayan Rajendran, Milos Doroslovacki, Guru Venkataramani
DFS covert channels on multi-core platforms. VLSI-SoC (2017)
Yujie Wang, Tri Cao, Jiang Hu, Jeyavijayan Rajendran
Front-end-of-line attacks in split manufacturing. ICCAD (2017)
Muhammad Yasin, Ozgur Sinanoglu, Jeyavijayan Rajendran
Testing the Trustworthiness of IC Testing: An Oracle-Less Attack on IC Camouflaging. IEEE Trans. Inf. Forensics Secur. 12 (11) (2017)
Muhammad Yasin, Abhrajit Sengupta, Mohammed Thari Nabeel, Mohammed Ashraf, Jeyavijayan Rajendran, Ozgur Sinanoglu
Provably-Secure Logic Locking: From Theory To Practice. CCS (2017)
Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran
Security analysis of Anti-SAT. ASP-DAC (2017)
Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran
Removal Attacks on Logic Locking and Camouflaging Techniques. IACR Cryptol. ePrint Arch. 2017 (2017)
Lang Feng, Yujie Wang, Jiang Hu, Wai-Kei Mak, Jeyavijayan Rajendran
Making split fabrication synergistically secure and manufacturable. ICCAD (2017)
Muhammad Yasin, Abhrajit Sengupta, Benjamin Carrión Schäfer, Yiorgos Makris, Ozgur Sinanoglu, Jeyavijayan Rajendran
What to Lock?: Functional and Parametric Locking. ACM Great Lakes Symposium on VLSI (2017)
Lang Feng, Yujie Wang, Jiang Hu, Wai-Kei Mak, Jeyavijayan Rajendran
Making split fabrication synergistically secure and manufacturable. ICCAD (2017)
Giovanni Di Crescenzo, Jeyavijayan Rajendran, Ramesh Karri, Nasir D. Memon
Boolean Circuit Camouflage: Cryptographic Models, Limitations, Provable Results and a Random Oracle Realization. ASHES@CCS (2017)
Jeyavijayan Rajendran, Jack Tang, Ramesh Karri
Securing pressure measurements using SensorPUFs. ISCAS (2016)
Yujie Wang, Pu Chen, Jiang Hu, Jeyavijayan Rajendran
The cat and mouse in split manufacturing. DAC (2016)
Arun K. Kanuparthi, Jeyavijayan Rajendran, Ramesh Karri
Controlling your control flow graph. HOST (2016)
Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran
Security Analysis of Anti-SAT. IACR Cryptol. ePrint Arch. 2016 (2016)
Mohammad-Mahdi Bidmeshki, Gaurav Rajavendra Reddy, Liwei Zhou, Jeyavijayan Rajendran, Yiorgos Makris
Hardware-based attacks to compromise the cryptographic security of an election system. ICCD (2016)
Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran
CamoPerturb: secure IC camouflaging for minterm protection. ICCAD (2016)
Jeyavijayan Rajendran, Arunshankar Muruga Dhandayuthapany, Vivekananda Vedula, Ramesh Karri
Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage. VLSI Design (2016)
Muhammad Yasin, Ozgur Sinanoglu, Jeyavijayan Rajendran
Testing the Trustworthiness of IC Testing: An Oracle-less Attack on IC Camouflaging. IACR Cryptol. ePrint Arch. 2016 (2016)
Chaofei Yang, Beiye Liu, Hai Li, Yiran Chen, Wujie Wen, Mark Barnell, Qing Wu, Jeyavijayan Rajendran
Security of neuromorphic computing: thwarting learning attacks using memristor's obsolescence effect. ICCAD (2016)
Md. Badruddoja Majumder, Mesbah Uddin, Garrett S. Rose, Jeyavijayan Rajendran
Sneak path enabled authentication for memristive crossbar memories. AsianHOST (2016)
Sk Subidh Ali, Mohamed Ibrahim, Jeyavijayan Rajendran, Ozgur Sinanoglu, Krishnendu Chakrabarty
Supply-Chain Security of Digital Microfluidic Biochips. Computer 49 (8) (2016)
Muhammad Yasin, Samah Mohamed Saeed, Jeyavijayan Rajendran, Ozgur Sinanoglu
Activation of logic encrypted chips: Pre-test or post-test? DATE (2016)
Jeyavijayan Rajendran, Huan Zhang, Chi Zhang, Garrett S. Rose, Youngok K. Pino, Ozgur Sinanoglu, Ramesh Karri
Fault Analysis-Based Logic Encryption. IEEE Trans. Computers 64 (2) (2015)
Jeyavijayan Rajendran, Aman Ali, Ozgur Sinanoglu, Ramesh Karri
Belling the CAD: Toward Security-Centric Electronic System Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (11) (2015)
Jeyavijayan Rajendran, Ramesh Karri, Garrett S. Rose
Improving Tolerance to Variations in Memristor-Based Applications Using Parallel Memristors. IEEE Trans. Computers 64 (3) (2015)
Jeyavijayan Rajendran, Vivekananda Vedula, Ramesh Karri
Detecting malicious modifications of data in third-party intellectual property cores. DAC (2015)
Jeyavijayan Rajendran, Ramesh Karri, James B. Wendt, Miodrag Potkonjak, Nathan R. McDonald, Garrett S. Rose, Bryant T. Wysocki
Nano Meets Security: Exploring Nanoelectronic Devices for Security Applications. Proc. IEEE 103 (5) (2015)
Adam Waksman, Jeyavijayan Rajendran, Matthew Suozzo, Simha Sethumadhavan
A Red Team/Blue Team Assessment of Functional Analysis Methods for Malicious Circuit Identification. DAC (2014)
Suriya Natarajan, Amitava Majumdar, Jeyavijayan Rajendran
Hot topic session 9C: Test and fault tolerance for emerging memory technologies. VTS (2014)
Davood Shahrjerdi, Jeyavijayan Rajendran, Siddharth Garg, Farinaz Koushanfar, Ramesh Karri
Shielding and securing integrated circuits with sensors. ICCAD (2014)
Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri
Regaining Trust in VLSI Design: Design-for-Trust Techniques. Proc. IEEE 102 (8) (2014)
David H. K. Hoe, Jeyavijayan Rajendran, Ramesh Karri
Towards Secure Analog Designs: A Secure Sense Amplifier Using Memristors. ISVLSI (2014)
Chen Liu, Jeyavijayan Rajendran, Chengmo Yang, Ramesh Karri
Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security- Driven Task Scheduling. IEEE Trans. Emerg. Top. Comput. 2 (4) (2014)
Jeyavijayan Rajendran, Huan Zhang, Ozgur Sinanoglu, Ramesh Karri
High-level synthesis for security and trust. IOLTS (2013)
Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri
VLSI testing based security metric for IC camouflaging. ITC (2013)
Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri
Is split manufacturing secure? DATE (2013)
Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu
Sneak-path Testing of Memristor-based Memories. VLSI Design (2013)
Masoud Rostami, Farinaz Koushanfar, Jeyavijayan Rajendran, Ramesh Karri
Hardware security: threat models and metrics. ICCAD (2013)
Ozgur Sinanoglu, Naghmeh Karimi, Jeyavijayan Rajendran, Ramesh Karri, Yier Jin, K. Huang, Yiorgos Makris
Reconciling the IC test and security dichotomy. ETS (2013)
Chen Liu, Jeyavijayan Rajendran, Chengmo Yang, Ramesh Karri
Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling. DFTS (2013)
Garrett S. Rose, Jeyavijayan Rajendran, Nathan R. McDonald, Ramesh Karri, Miodrag Potkonjak, Bryant T. Wysocki
Hardware security strategies exploiting nanoelectronic circuits. ASP-DAC (2013)
Xuehui Zhang, Kan Xiao, Mohammad Tehranipoor, Jeyavijayan Rajendran, Ramesh Karri
A study on the effectiveness of Trojan detection techniques using a red team blue team approach. VTS (2013)
Jeyavijayan Rajendran, Michael Sam, Ozgur Sinanoglu, Ramesh Karri
Security analysis of integrated circuit camouflaging. CCS (2013)
Jeyavijayan Rajendran, Arun K. Kanuparthi, Mohamed Zahran, Sateesh Addepalli, Gaston Ormazabal, Ramesh Karri
Securing Processors Against Insider Attacks: A Circuit-Microarchitecture Co-Design Approach. IEEE Des. Test 30 (2) (2013)
Jeyavijayan Rajendran, Ramesh Karri, James B. Wendt, Miodrag Potkonjak, Nathan R. McDonald, Garrett S. Rose, Bryant T. Wysocki
Nanoelectronic Solutions for Hardware Security. IACR Cryptol. ePrint Arch. 2012 (2012)
Jeyavijayan Rajendran, Youngok K. Pino, Ozgur Sinanoglu, Ramesh Karri
Logic encryption: A fault analysis perspective. DATE (2012)
Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose
An Energy-Efficient Memristive Threshold Logic Circuit. IEEE Trans. Computers 61 (4) (2012)
Garrett S. Rose, Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Robinson E. Pino
Leveraging Memristive Systems in the Construction of Digital Logic Circuits. Proc. IEEE 100 (6) (2012)
Jeyavijayan Rajendran, Garrett S. Rose, Ramesh Karri, Miodrag Potkonjak
Nano-PPUF: A Memristor-Based Security Primitive. ISVLSI (2012)
Harika Manem, Jeyavijayan Rajendran, Garrett S. Rose
Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2012)
Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu
Engineering crossbar based emerging memory technologies. ICCD (2012)

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Publication Activity (10 Years)

Top Topics

Top Venues

Jeyavijayan Rajendran