Samah Mohamed Saeed

Publication Activity (10 Years)

Years Active: 2010-2024
Publications (10 Years): 28

Top Topics

Countermeasures

Logic Synthesis

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Christian Rasmussen, Samah Mohamed Saeed
Time-Aware Re-Synthesis for Secure Quantum Systems. HOST (2024)
Vedika Saravanan, Samah Mohamed Saeed
Noise Adaptive Quantum Circuit Mapping Using Reinforcement Learning and Graph Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (5) (2024)
Vedika Saravanan, Mohammad Walid Charrwi, Samah Mohamed Saeed
Revisiting Trojan Insertion Techniques for Post-Silicon Trojan Detection Evaluation. ISVLSI (2023)
Vedika Saravanan, Samah Mohamed Saeed
Data-Driven Reliability Models of Quantum Circuit: From Traditional ML to Graph Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (5) (2023)
Vedika Saravanan, Samah Mohamed Saeed
Machine Learning for Quantum Hardware Performance Assessment. ICCD (2022)
Vedika Servanan, Samah Mohamed Saeed
Graph Neural Networks for Idling Error Mitigation. ICCAD (2022)
Vedika Saravanan, Samah Mohamed Saeed
Pauli Error Propagation-Based Gate Reschedulingfor Quantum Circuit Error Mitigation. CoRR (2022)
Nikita Acharya, Miroslav Urbánek, Wibe A. de Jong, Samah Mohamed Saeed
Test Points for Online Monitoring of Quantum Circuits. ACM J. Emerg. Technol. Comput. Syst. 18 (1) (2022)
Mohammad Walid Charrwi, Huy Phan, Bo Yuan, Samah Mohamed Saeed
Towards Yield Improvement for AI Accelerators: Analysis and Exploration. ISVLSI (2022)
Vedika Saravanan, Samah Mohamed Saeed
Decomposition-Based Watermarking of Quantum Circuits. ISQED (2021)
Vedika Saravanan, Samah Mohamed Saeed
Test Data-Driven Machine Learning Models for Reliable Quantum Circuit Output. ETS (2021)
Nikita Acharya, Samah Mohamed Saeed
Automated Flag Qubit Insertion for Reliable Quantum Circuit Output. ISVLSI (2021)
Reginald Tetteh, Samah Mohamed Saeed
Analysis of Test Data Tampering Attack on Manufacturing Testing. DTIS (2020)
Nikita Acharya, Vedika Saravanan, Samah Mohamed Saeed
An Attack on Quantum Circuits Based on the Error Rates of NISQ Systems and a Countermeasure. SVCC (2020)
Xiaotong Cui, Samah Mohamed Saeed, Alwin Zulehner, Robert Wille, Kaijie Wu, Rolf Drechsler, Ramesh Karri
On the Difficulty of Inserting Trojans in Reversible Computing Architectures. IEEE Trans. Emerg. Top. Comput. 8 (4) (2020)
Nikita Acharya, Samah Mohamed Saeed
A Lightweight Approach to Detect Malicious/Unexpected Changes in the Error Rates of NISQ Computers. ICCAD (2020)
Samah Mohamed Saeed, Robert Wille, Ramesh Karri
Locking the Design of Building Blocks for Quantum Circuits. ACM Trans. Embed. Comput. Syst. 18 (5s) (2019)
Samah Mohamed Saeed, Nithin Mahendran, Alwin Zulehner, Robert Wille, Ramesh Karri
Identification of Synthesis Approaches for IP/IC Piracy of Reversible Circuits. ACM J. Emerg. Technol. Comput. Syst. 15 (3) (2019)
Kanad Basu, Samah Mohamed Saeed, Christian Pilato, Mohammed Ashraf, Mohammed Thari Nabeel, Krishnendu Chakrabarty, Ramesh Karri
CAD-Base: An Attack Vector into the Electronics Supply Chain. ACM Trans. Design Autom. Electr. Syst. 24 (4) (2019)
Samah Mohamed Saeed, Alwin Zulehner, Robert Wille, Rolf Drechsler, Ramesh Karri
Reversible Circuits: IC/IP Piracy Attacks and Countermeasures. IEEE Trans. Very Large Scale Integr. Syst. 27 (11) (2019)
Samah Mohamed Saeed, Xiaotong Cui, Alwin Zulehner, Robert Wille, Rolf Drechsler, Kaijie Wu, Ramesh Karri
IC/IP piracy assessment of reversible logic. ICCAD (2018)
Bodhisatwa Mazumdar, Samah Mohamed Saeed, Sk Subidh Ali, Ozgur Sinanoglu
Timing Attack and Countermeasure on NEMS Relay Based Design of Block Ciphers. IEEE Trans. Emerg. Top. Comput. 5 (3) (2017)
Samah Mohamed Saeed, Xiaotong Cui, Robert Wille, Alwin Zulehner, Kaijie Wu, Rolf Drechsler, Ramesh Karri
Towards Reverse Engineering Reversible Logic. CoRR (2017)
Samah Mohamed Saeed, Nithin Mahendran, Alwin Zulehner, Robert Wille, Ramesh Karri
Identifying Reversible Circuit Synthesis Approaches to Enable IP Piracy Attacks. ICCD (2017)
Xiaotong Cui, Samah Mohamed Saeed, Alwin Zulehner, Robert Wille, Rolf Drechsler, Kaijie Wu, Ramesh Karri
On the Difficulty of Inserting Trojans in Reversible Computing Architectures. CoRR (2017)
Samah Mohamed Saeed, Ozgur Sinanoglu
A Comprehensive Design-for-Test Infrastructure in the Context of Security-Critical Applications. IEEE Des. Test 34 (1) (2017)
Bodhisatwa Mazumdar, Samah Mohamed Saeed, Sk Subidh Ali, Ozgur Sinanoglu
Thwarting timing attacks on NEMS relay based designs. VTS (2016)
Muhammad Yasin, Samah Mohamed Saeed, Jeyavijayan Rajendran, Ozgur Sinanoglu
Activation of logic encrypted chips: Pre-test or post-test? DATE (2016)
Sk Subidh Ali, Samah Mohamed Saeed, Ozgur Sinanoglu, Ramesh Karri
Novel Test-Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (5) (2015)
Samah Mohamed Saeed, Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu
Timing attack on NEMS relay based design of AES. VLSI-SoC (2015)
Sk Subidh Ali, Ozgur Sinanoglu, Samah Mohamed Saeed, Ramesh Karri
New scan attacks against state-of-the-art countermeasures and DFT. HOST (2014)
Samah Mohamed Saeed, Ozgur Sinanoglu
Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing. IEEE Trans. Very Large Scale Integr. Syst. 22 (3) (2014)
Abishek Ramdas, Samah Mohamed Saeed, Ozgur Sinanoglu
Slack removal for enhanced reliability and trust. DTIS (2014)
Samah Mohamed Saeed, Sk Subidh Ali, Ozgur Sinanoglu, Ramesh Karri
Test-mode-only scan attack and countermeasure for contemporary scan architectures. ITC (2014)
Samah Mohamed Saeed
DfST: Design for secure testability. ITC (2014)
Sk Subidh Ali, Samah Mohamed Saeed, Ozgur Sinanoglu, Ramesh Karri
New Scan-Based Attack Using Only the Test Mode and an Input Corruption Countermeasure. VLSI-SoC (Selected Papers) (2013)
Sk Subidh Ali, Ozgur Sinanoglu, Samah Mohamed Saeed, Ramesh Karri
New scan-based attack using only the test mode. VLSI-SoC (2013)
Samah Mohamed Saeed, Ozgur Sinanoglu
Expedited-compact architecture for average scan power reduction. IEEE Des. Test 30 (3) (2013)
Samah Mohamed Saeed, Ozgur Sinanoglu, Sobeeh Almukhaizim
Predictive Techniques for Projecting Test Data Volume Compression. IEEE Trans. Very Large Scale Integr. Syst. 21 (9) (2013)
Sk Subidh Ali, Samah Mohamed Saeed, Ozgur Sinanoglu, Ramesh Karri
Scan attack in presence of mode-reset countermeasure. IOLTS (2013)
Samah Mohamed Saeed, Ozgur Sinanoglu
DfT support for launch and capture power reduction in launch-off-capture testing. ETS (2012)
Samah Mohamed Saeed, Ozgur Sinanoglu
Multi-modal response compaction adaptive to x-density variation. IET Comput. Digit. Tech. 6 (2) (2012)
Samah Mohamed Saeed, Ozgur Sinanoglu
Expedited response compaction for scan power reduction. VTS (2011)
Samah Mohamed Saeed, Ozgur Sinanoglu
XOR-Based Response Compactor Adaptive to X-Density Variation. Asian Test Symposium (2010)