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Harika Manem
Publication Activity (10 Years)
Years Active: 2008-2018
Publications (10 Years): 4
Top Topics
Logic Circuits
Design Considerations
Random Access Memory
Stochastic Gradient Descent
Top Venues
ACM J. Emerg. Technol. Comput. Syst.
IEEE Trans. Circuits Syst. I Regul. Pap.
CISDA
Proc. IEEE
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Publications
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Mesbah Uddin
,
Md. Badruddoja Majumder
,
Karsten Beckmann
,
Harika Manem
,
Zahiruddin Alamgir
,
Nathaniel C. Cady
,
Garrett S. Rose
Design Considerations for Memristive Crossbar Physical Unclonable Functions.
ACM J. Emerg. Technol. Comput. Syst.
14 (1) (2018)
Karsten Beckmann
,
Harika Manem
,
Nathaniel C. Cady
Performance Enhancement of a Time-Delay PUF Design by Utilizing Integrated Nanoscale ReRAM Devices.
IEEE Trans. Emerg. Top. Comput.
5 (3) (2017)
Mesbah Uddin
,
Md. Badruddoja Majumder
,
Garrett S. Rose
,
Karsten Beckmann
,
Harika Manem
,
Zahiruddin Alamgir
,
Nathaniel C. Cady
Techniques for Improved Reliability in Memristive Crossbar PUF Circuits.
ISVLSI
(2016)
Harika Manem
,
Karsten Beckmann
,
Min Xu
,
Robert Carroll
,
Robert E. Geer
,
Nathaniel C. Cady
An extendable multi-purpose 3D neuromorphic fabric using nanoscale memristors.
CISDA
(2015)
Jeyavijayan Rajendran
,
Harika Manem
,
Ramesh Karri
,
Garrett S. Rose
An Energy-Efficient Memristive Threshold Logic Circuit.
IEEE Trans. Computers
61 (4) (2012)
Garrett S. Rose
,
Jeyavijayan Rajendran
,
Harika Manem
,
Ramesh Karri
,
Robinson E. Pino
Leveraging Memristive Systems in the Construction of Digital Logic Circuits.
Proc. IEEE
100 (6) (2012)
Harika Manem
,
Jeyavijayan Rajendran
,
Garrett S. Rose
Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array.
IEEE Trans. Circuits Syst. I Regul. Pap.
(5) (2012)
Harika Manem
,
Jeyavijayan Rajendran
,
Garrett S. Rose
Design Considerations for Multilevel CMOS/Nano Memristive Memory.
ACM J. Emerg. Technol. Comput. Syst.
8 (1) (2012)
Jeyavijayan Rajendran
,
Harika Manem
,
Ramesh Karri
,
Garrett S. Rose
An Approach to Tolerate Process Related Variations in Memristor-Based Applications.
VLSI Design
(2011)
Harika Manem
,
Garrett S. Rose
A read-monitored write circuit for 1T1M multi-level memristor memories.
ISCAS
(2011)
Harika Manem
,
Garrett S. Rose
,
Xiaoli He
,
Wei Wang
Design considerations for variation tolerant multilevel CMOS/Nano memristor memory.
ACM Great Lakes Symposium on VLSI
(2010)
Jeyavijayan Rajendran
,
Harika Manem
,
Ramesh Karri
,
Garrett S. Rose
Memristor based programmable threshold logic array.
NANOARCH
(2010)
Benjamin Gojman
,
Harika Manem
,
Garrett S. Rose
,
André DeHon
Inversion schemes for sublithographic programmable logic arrays.
IET Comput. Digit. Tech.
3 (6) (2009)
Harika Manem
,
Garrett S. Rose
The effects of logic partitioning in a majority logic based CMOS-NANO FPGA.
ACM Great Lakes Symposium on VLSI
(2009)
Harika Manem
,
Peter C. Paliwoda
,
Garrett S. Rose
A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays.
ACM Great Lakes Symposium on VLSI
(2008)