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Design Considerations for Multilevel CMOS/Nano Memristive Memory.
Harika Manem
Jeyavijayan Rajendran
Garrett S. Rose
Published in:
ACM J. Emerg. Technol. Comput. Syst. (2012)
Keyphrases
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design considerations
random access memory
low voltage
nano scale
high speed
memory requirements
real time
neural network
data storage
pedagogical agents
random access
memory size