Chandan Karfa

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 43

Top Topics

Reverse Engineer

Genetic Algorithm

Distributed Systems

Functional Verification

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Bhabesh Mali, Karthik Maddala, Sweeya Reddy, Vatsal Gupta, Chandan Karfa, Ramesh Karri
ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generation. CoRR (2024)
Praveen Karmakar, Marpina Bharani, Chandan Karfa
Evaluating the Robustness of Large scale eFPGA-based Hardware Redaction. VLSID (2024)
Nilotpola Sarma, Anuj Singh Thakur, Chandan Karfa
MaskedHLS: Domain-Specific High-Level Synthesis of Masked Cryptographic Designs. CoRR (2024)
Priyanka Panigrahi, Vignesh Ravichandra Rao, Thockchom Birjit Singha, Chandan Karfa
SRIL: Securing Registers from Information Leakage at Register Transfer Level. VLSID (2024)
Debabrata Senapati, Dharmendra Maurya, Arnab Sarkar, Chandan Karfa
ERS: Energy-efficient Real-time DAG Scheduling on Uniform Multiprocessor Embedded Systems. VLSID (2024)
Surajit Das, Hetang Patel, Chandan Karfa, Kartheek Bellamkonda, Rahul Reddy, Disha Puri, Anshul Jain, Arijit Sur, Pradip Prajapati
RTL Simulation Acceleration with Machine Learning Models. ISQED (2024)
Debabrata Senapati, Kousik Rajesh, Chandan Karfa, Arnab Sarkar
TMDS: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems. ACM Trans. Design Autom. Electr. Syst. 28 (6) (2023)
Debabrata Senapati, Arnab Sarkar, Chandan Karfa
Energy-Aware Real-Time Scheduling of Multiple Periodic DAGs on Heterogeneous Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (8) (2023)
Priyanka Panigrahi, Chandan Karfa
An Investigation into the Security of Register Allocation with Spilling and Splitting. ISVLSI (2023)
Priyanka Panigrahi, Chandan Karfa
Translation Validation of Information Leakage of Compiler Optimizations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (11) (2023)
Priyanka Panigrahi, Abhik Paul, Chandan Karfa
Quantifying Information Leakage for Security Verification of Compiler Optimizations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Abdul Khader Thalakkattu Moosa, Nilotpola Sarma, Chandan Karfa
ImageSpec: Efficient High-Level Synthesis of Image Processing Applications. DSD (2022)
Surajit Das, Chandan Karfa, Santosh Biswas
Accelerating NoC Verification Using a Complete Model and Active Window. IEEE Access 10 (2022)
Mohammed Abderehman, Jayprakash Patidar, Jay H. Oza, Yom Nigam, T. M. Abdul Khader, Chandan Karfa
FastSim: A Fast Simulation Framework for High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (5) (2022)
Surajit Das, Chandan Karfa
Arc Model and DDG: Deadlock Avoidance and Detection in Torus NoC. IEEE Embed. Syst. Lett. 14 (2) (2022)
Debabrata Senapati, Arnab Sarkar, Chandan Karfa
PRESTO: A Penalty-Aware Real-Time Scheduler for Task Graphs on Heterogeneous Platforms. IEEE Trans. Computers 71 (2) (2022)
Mohammed Abderehman, Theegala Rakesh Reddy, Chandan Karfa
DEEQ: Data-driven End-to-End EQuivalence Checking of High-level Synthesis. ISQED (2022)
Arshdeep Kaur, Sayandeep Saha, Chandan Karfa, Debdeep Mukhopadhyay
Corruption Exposes You: Statistical Key Recovery from Compound Logic Locking. ISQED (2022)
Priyanka Panigrahi, Vemuri Sahithya, Chandan Karfa, Prabhat Mishra
Secure Register Allocation for Trusted Code Generation. IEEE Embed. Syst. Lett. 14 (3) (2022)
Gagan Gayari, Chandan Karfa, Prithwijit Guha
GAUR: Genetic Algorithm based Unlocking of Register Transfer Level Locking. ACM Great Lakes Symposium on VLSI (2022)
Debabrata Senapati, Arnab Sarkar, Chandan Karfa
Performance-Effective DAG Scheduling for Heterogeneous Distributed Systems. ICDCN (2022)
Mohammed Abderehman, Rupak Gupta, Theegala Rakesh Reddy, Chandan Karfa
BLAST: Belling the Black-Hat High-Level Synthesis Tool. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Mohammed Abderehman, Rupak Gupta, Chandan Karfa
Reverse Engineering Register to Variable Mapping in High-level Synthesis. ISVLSI (2021)
Chandan Karfa, T. M. Abdul Khader, Yom Nigam, Ramanuj Chouksey, Ramesh Karri
HOST: HLS Obfuscations against SMT ATtack. DATE (2021)
Ramanuj Chouksey, Sachin Kumar Maddheshiya, Chandan Karfa
VP_TT: A value propagation based equivalence checker for testability transformations. IET Softw. 15 (1) (2021)
Debabrata Senapati, Arnab Sarkar, Chandan Karfa
HMDS: A Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems. ACM Trans. Embed. Comput. Syst. 20 (5s) (2021)
Melbin John, Aadil Hoda, Ramanuj Chouksey, Chandan Karfa
SAT Based Partial Attack on Compound Logic Locking. AsianHOST (2020)
Surajit Das, Chandan Karfa, Santosh Biswas
Formal Modeling of Network-on-Chip Using CFSM and its Application in Detecting Deadlock. IEEE Trans. Very Large Scale Integr. Syst. 28 (4) (2020)
Benjamin Tan, Ramesh Karri, Nimisha Limaye, Abhrajit Sengupta, Ozgur Sinanoglu, Md Moshiur Rahman, Swarup Bhunia, Danielle Duvalsaint, Ronald D. Blanton, Amin Rezaei, Yuanqi Shen, Hai Zhou, Leon Li, Alex Orailoglu, Zhaokun Han, Austin Benedetti, Luciano Brignone, Muhammad Yasin, Jeyavijayan Rajendran, Michael Zuzak, Ankur Srivastava, Ujjwal Guin, Chandan Karfa, Kanad Basu, Vivek V. Menon, Matthew French, Peilin Song, Franco Stellari, Gi-Joon Nam, Peter Gadfort, Alric Althoff, Joseph Tostenrude, Saverio Fazzari, Eric Breckenfeld, Kenneth Plaks
Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking. CoRR (2020)
Ramanuj Chouksey, Chandan Karfa
Verification of Scheduling of Conditional Behaviors in High-Level Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 28 (7) (2020)
Pankaj Kumar Kalita, Ramanuj Chouksey, Chandan Karfa
Automatic Inverse Operation Detection and its Impact in High-level Synthesis. VDAT (2020)
Chandan Karfa, Ramanuj Chouksey, Christian Pilato, Siddharth Garg, Ramesh Karri
Is Register Transfer Level Locking Secure? DATE (2020)
Ramanuj Chouksey, Chandan Karfa, Purandar Bhaduri
Translation Validation of Code Motion Transformations Involving Loops. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (7) (2019)
Priyanka Panigrahi, Rajesh Kumar Jha, Chandan Karfa
User Guided Register Manipulation in Digital Circuits. VDAT (2019)
Ramanuj Chouksey, Chandan Karfa, Purandar Bhaduri
Formal Verification of Optimizing Transformations during High-level Synthesis. ISEC (2019)
Kunal Banerjee, Chandan Karfa
A Quick Introduction to Functional Verification of Array-Intensive Programs. CoRR (2019)
Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal
Verification of parallelising transformations of KPN models. IET Cyper-Phys. Syst.: Theory & Appl. 4 (3) (2019)
Ramanuj Chouksey, Chandan Karfa, Purandar Bhaduri
Improving Performance of a Path-Based Equivalence Checker Using Counter-Examples. VLSI Design (2019)
Ramanuj Chouksey, Chandan Karfa, Kunal Banerjee, Pankaj Kumar Kalita, Purandar Bhaduri
Counter-example generation procedure for path-based equivalence checkers. IET Softw. 13 (4) (2019)
Kunal Banerjee, Ramanuj Chouksey, Chandan Karfa, Pankaj Kumar Kalita
Automatic detection of inverse operations while avoiding loop unrolling. ICSE (Companion Volume) (2018)
Kunal Banerjee, Chandan Karfa
Compiler-agnostic Translation Validation. ISEC (2018)
Surajit Das, Chandan Karfa, Santosh Biswas
xMAS Based Accurate Modeling and Progress Verification of NoCs. VDAT (2017)
Ramanuj Chouksey, Chandan Karfa, Purandar Bhaduri
Translation Validation of Loop Invariant Code Optimizations Involving False Computations. VDAT (2017)
Kunal Banerjee, Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal
Verification of Code Motion Techniques Using Value Propagation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (8) (2014)
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal
Verification of KPN Level Transformations. VLSI Design (2013)
Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal
Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (11) (2013)
Kunal Banerjee, Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal
A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques. ISED (2012)
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar
Formal verification of code motion techniques using data-flow-driven equivalence checking. ACM Trans. Design Autom. Electr. Syst. 17 (3) (2012)
Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chitta Mandal
Equivalence Checking of Array-Intensive Programs. ISVLSI (2011)
Chandan Karfa, Chitta Mandal, Dipankar Sarkar
Verification of Register Transfer Level Low Power Transformations. ISVLSI (2011)
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal
Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques. ISVLSI (2010)
Chandan Karfa, Dipankar Sarkar, Chitta Mandal
Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (3) (2010)
Chandan Karfa, Dipankar Sarkar, Chitta Mandal, P. Kumar
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (3) (2008)
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, Chris Reade
Hand-in-hand verification of high-level synthesis. ACM Great Lakes Symposium on VLSI (2007)
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, Chris Reade
Register Sharing Verification During Data-Path Synthesis. ICCTA (2007)
Santosh Biswas, Chandan Karfa, Himani Kanwar, Dipankar Sarkar, Siddhartha Mukhopadhyay, Amit Patra
Fairness of transitions in diagnosability analysis of hybrid systems. ACC (2006)
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade
Verification of Scheduling in High-level Synthesis. ISVLSI (2006)
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade
A Formal Verification Method of Scheduling in High-level Synthesis. ISQED (2006)